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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-05-09 17:56:03 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-05-29 10:16:56 +0000
commit84ba92ed750ce7b4183f6c2054dbf60d498053c6 (patch)
tree8a4cf97ad4ee7e10a7b034c5d43eba4af8f8e609 /src
parent97c33d677f0130116ca40ca2e54a6aec7ad14961 (diff)
downloadgem5-84ba92ed750ce7b4183f6c2054dbf60d498053c6.tar.xz
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool of implementation defined registers, provided that reg numbers are in the following range: <op1> is in the range 0 - 7 <CRn> can take the values 11, 15 <CRm> is in the range 0 - 15 <op2> is in the range 0 - 7 Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10501 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/miscregs.cc10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index e1ddbf9d3..08e37bb70 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2082,9 +2082,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
- break;
+ M5_FALLTHROUGH;
+ default:
+ // S3_<op1>_11_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
- break;
+ M5_UNREACHABLE;
case 12:
switch (op1) {
case 0:
@@ -2370,7 +2373,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
- break;
+ // S3_<op1>_15_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
break;
}