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| author | Chuan Zhu <chuan.zhu@arm.com> | 2017-12-29 20:04:14 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-18 15:22:52 +0000 |
| commit | abbe32b6acacb22761e969b716631c5f616f3229 (patch) | |
| tree | e6c07e896d773eb637c2fecf6c9ba074f9cce117 /src | |
| parent | b299740e655cb64d630aa72934dc47375f68910c (diff) | |
| download | gem5-abbe32b6acacb22761e969b716631c5f616f3229.tar.xz | |
arch-arm: Mask out unsupported trapped exception handling bits
Floating-point trapped exception handlings are not currently
supported in gem5, therefore the corresponding bits are RAZ/WI in
FCPR.
Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10045
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa.cc | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 347e644d1..954375374 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -521,12 +521,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) { const uint32_t ones = (uint32_t)(-1); FPSCR fpscrMask = 0; - fpscrMask.ioe = ones; - fpscrMask.dze = ones; - fpscrMask.ofe = ones; - fpscrMask.ufe = ones; - fpscrMask.ixe = ones; - fpscrMask.ide = ones; fpscrMask.len = ones; fpscrMask.stride = ones; fpscrMask.rMode = ones; @@ -865,12 +859,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { const uint32_t ones = (uint32_t)(-1); FPSCR fpscrMask = 0; - fpscrMask.ioe = ones; - fpscrMask.dze = ones; - fpscrMask.ofe = ones; - fpscrMask.ufe = ones; - fpscrMask.ixe = ones; - fpscrMask.ide = ones; fpscrMask.len = ones; fpscrMask.stride = ones; fpscrMask.rMode = ones; |