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authorSteve Reinhardt <stever@gmail.com>2008-02-26 20:17:26 -0800
committerSteve Reinhardt <stever@gmail.com>2008-02-26 20:17:26 -0800
commitbdf33239151c7fcc194f6f9b8c62eb313c933755 (patch)
tree813955010ce9920d1f550133c5a19216b066a745 /src
parent8c0baf2ce478b16d351feb1f0ce147049f3a04f6 (diff)
downloadgem5-bdf33239151c7fcc194f6f9b8c62eb313c933755.tar.xz
Cache: better comments particularly regarding writeback situation.
--HG-- extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/cache.hh24
-rw-r--r--src/mem/cache/cache_impl.hh18
2 files changed, 30 insertions, 12 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 6f5428c13..f5f65d4dd 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -270,12 +270,32 @@ class Cache : public BaseCache
void squash(int threadNum);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Generate an appropriate downstream bus request packet for the
+ * given parameters.
+ * @param cpu_pkt The upstream request that needs to be satisfied.
+ * @param blk The block currently in the cache corresponding to
+ * cpu_pkt (NULL if none).
+ * @param needsExclusive Indicates that an exclusive copy is required
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @return A new Packet containing the request, or NULL if the
+ * current request in cpu_pkt should just be forwarded on.
*/
PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
bool needsExclusive);
+
+ /**
+ * Return the next MSHR to service, either a pending miss from the
+ * mshrQueue, a buffered write from the write buffer, or something
+ * from the prefetcher. This function is responsible for
+ * prioritizing among those sources on the fly.
+ */
MSHR *getNextMSHR();
+
+ /**
+ * Selects an outstanding request to service. Called when the
+ * cache gets granted the downstream bus in timing mode.
+ * @return The request to service, NULL if none found.
+ */
PacketPtr getTimingPacket();
/**
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d4fbc90a5..15de76532 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -439,12 +439,12 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
#if 0
+ /** @todo make the fast write alloc (wh64) work with coherence. */
+
PacketList writebacks;
// If this is a block size write/hint (WH64) allocate the block here
// if the coherence protocol allows it.
- /** @todo make the fast write alloc (wh64) work with coherence. */
- /** @todo Do we want to do fast writes for writebacks as well? */
if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
(pkt->cmd == MemCmd::WriteReq
|| pkt->cmd == MemCmd::WriteInvalidateReq) ) {
@@ -517,6 +517,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
+// See comment in cache.hh.
template<class TagStore>
PacketPtr
Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
@@ -529,14 +530,11 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
return NULL;
}
- if (!blkValid &&
- (cpu_pkt->cmd == MemCmd::Writeback ||
- cpu_pkt->cmd == MemCmd::UpgradeReq)) {
- // For now, writebacks from upper-level caches that
- // completely miss in the cache just go through. If we had
- // "fast write" support (where we could write the whole
- // block w/o fetching new data) we might want to allocate
- // on writeback misses instead.
+ if (!blkValid && (cpu_pkt->cmd == MemCmd::Writeback ||
+ cpu_pkt->cmd == MemCmd::UpgradeReq)) {
+ // Writebacks that weren't allocated in access() and upgrades
+ // from upper-level caches that missed completely just go
+ // through.
return NULL;
}