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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
commit | cae870eded4b40b23990a232510c7914b12a9e86 (patch) | |
tree | 64b93f451d213d06b7fbe36b4f73df1586e68a46 /src | |
parent | 311f77f33d8a4f59421d4bb740e328ce3b86ea33 (diff) | |
download | gem5-cae870eded4b40b23990a232510c7914b12a9e86.tar.xz |
ARM: Get rid of end_addr in the ArmMacroStore constructor.
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index df52f9413..e50e31386 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -52,9 +52,7 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) { %(constructor)s; uint32_t regs_to_handle = reglist; - uint32_t j = 0, - start_addr = 0, - end_addr = 0; + uint32_t start_addr = 0; switch (puswl) { @@ -63,28 +61,24 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) case 0x02: // W stmda_w case 0x03: // WL ldmda_wl start_addr = (ones << 2) - 4; - end_addr = 0; break; case 0x08: // U stmia_u case 0x09: // U L ldmia_ul case 0x0a: // U W stmia case 0x0b: // U WL ldmia start_addr = 0; - end_addr = (ones << 2) - 4; break; case 0x10: // P stmdb case 0x11: // P L ldmdb case 0x12: // P W stmdb case 0x13: // P WL ldmdb start_addr = (ones << 2); // U-bit is already 0 for subtract - end_addr = 4; // negative 4 break; case 0x18: // PU stmib case 0x19: // PU L ldmib case 0x1a: // PU W stmib case 0x1b: // PU WL ldmib start_addr = 4; - end_addr = (ones << 2) + 4; break; default: panic("Unhandled Load/Store Multiple Instruction, " @@ -92,12 +86,11 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) break; } - //TODO - Add addi_uop/subi_uop here to create starting addresses - //Just using addi with 0 offset makes a "copy" of Rn for our use uint32_t newMachInst = 0; newMachInst = machInst & 0xffff0000; microOps[0] = new Addi_uop(newMachInst); + unsigned j = 0; for (int i = 1; i < ones+1; i++) { // Get next available bit for transfer @@ -113,15 +106,6 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) start_addr -= 4; } - /* TODO: Take a look at how these 2 values should meet together - if (start_addr != (end_addr - 4)) - { - fprintf(stderr, "start_addr: %d\n", start_addr); - fprintf(stderr, "end_addr: %d\n", end_addr); - panic("start_addr does not meet end_addr"); - } - */ - if (writeback) { uint32_t newMachInst = machInst & 0xf0000000; |