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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:07:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:07:55 -0700 |
| commit | da2df2fc251440d0dbd91864d74ba94a2153ca5e (patch) | |
| tree | d9ace5aaeb0b6ac438a0f46dcc85f6aa37a39bf2 /src | |
| parent | b64d0bdeda1662091746c3695b4429fcc6f69342 (diff) | |
| download | gem5-da2df2fc251440d0dbd91864d74ba94a2153ca5e.tar.xz | |
X86: Make conditional moves zero extend their 32 bit destinations always.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 6921684a4..dc6819886 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -639,7 +639,7 @@ let {{ class Mov(CondRegOp): code = 'DestReg = merge(SrcReg1, op2, dataSize)' - else_code = 'DestReg=DestReg;' + else_code = 'DestReg = merge(DestReg, DestReg, dataSize);' # Shift instructions |