Another merge with the main repository.

59 files changed, 222 insertions, 159 deletions

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index e276833e2..875ceae31 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -156,18 +156,23 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     // Regular int regs
     for (int i = 0; i < STATE_NUMVALS; i++) {
         if (nState.changed[i] || mState.changed[i]) {
-            const char *vergence = "  ";
             bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
             bool newMatch = (mState.newState[i] == nState.newState[i]);
             if (oldMatch && newMatch) {
                 // The more things change, the more they stay the same.
                 continue;
-            } else if (oldMatch && !newMatch) {
+            }
+
+            errorFound = true;
+
+#ifndef NDEBUG
+            const char *vergence = "  ";
+            if (oldMatch && !newMatch) {
                 vergence = "<>";
             } else if (!oldMatch && newMatch) {
                 vergence = "><";
             }
-            errorFound = true;
+
             if (!nState.changed[i]) {
                 DPRINTF(ExecRegDelta, "%s [%5s] "\
                                       "Native:         %#010x         "\
@@ -190,6 +195,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
                                       nState.oldState[i], nState.newState[i],
                                       mState.oldState[i], mState.newState[i]);
             }
+#endif
         }
     }
     if (errorFound) {
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 53f7f978e..ff65eb04c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -322,6 +322,9 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
                     DPRINTF(TLB, "Miss was serviced.\n");
                 }
             }
+
+            DPRINTF(TLB, "Entry found with paddr %#x, "
+                    "doing protection checks.\n", entry->paddr);
             // Do paging protection checks.
             bool inUser = (m5Reg.cpl == 3 &&
                     !(flags & (CPL0FlagBit << FlagShift)));
@@ -339,9 +342,6 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
                 return new PageFault(vaddr, true, Write, inUser, false);
             }
 
-
-            DPRINTF(TLB, "Entry found with paddr %#x, "
-                    "doing protection checks.\n", entry->paddr);
             Addr paddr = entry->paddr | (vaddr & (entry->size-1));
             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
             req->setPaddr(paddr);
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 77f793769..021ef3684 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -644,8 +644,7 @@ BaseRemoteGDB::trap(int type)
     bufferSize = gdbregs.bytes() * 2 + 256;
     buffer = (char*)malloc(bufferSize);
 
-    TheISA::PCState pc = context->pcState();
-    DPRINTF(GDBMisc, "trap: PC=%s\n", pc);
+    DPRINTF(GDBMisc, "trap: PC=%s\n", context->pcState());
 
     clearSingleStep();
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 686b40dc5..28fd434fe 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1051,8 +1051,8 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
 
         if (fetchStatus[tid] != Squashing) {
 
-            TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
-            DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
+            DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
+                fromDecode->decodeInfo[tid].nextPC);
             // Squash unless we're already squashing
             squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
                              fromDecode->decodeInfo[tid].squashInst,
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index d26bbf4ba..957aca19c 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -2118,11 +2118,12 @@ IGbE::txStateMachine()
     // iteration we'll get the rest of the data
     if (txPacket && txDescCache.packetAvailable()
         && !txDescCache.packetMultiDesc() && txPacket->length) {
-        bool success;
-
         anQ("TXS", "TX FIFO Q");
         DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
-        success = txFifo.push(txPacket);
+#ifndef NDEBUG
+        bool success =
+#endif
+            txFifo.push(txPacket);
         txFifoTick = true && !drainEvent;
         assert(success);
         txPacket = NULL;
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index 291ce1389..5a663bac9 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -490,6 +490,7 @@ IdeController::dispatchAccess(PacketPtr pkt, bool read)
         panic("IDE controller access to invalid address: %#x\n", addr);
     }
 
+#ifndef NDEBUG
     uint32_t data;
     if (pkt->getSize() == 1)
         data = pkt->get<uint8_t>();
@@ -499,6 +500,7 @@ IdeController::dispatchAccess(PacketPtr pkt, bool read)
         data = pkt->get<uint32_t>();
     DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
             read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
+#endif
 
     pkt->makeAtomicResponse();
 }
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index 942b835f0..f124767ca 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -142,13 +142,9 @@ DmaPort::recvTiming(PacketPtr pkt)
 
         pkt->reinitNacked();
         queueDma(pkt, true);
+    } else if (pkt->isRequest() && recvSnoops) {
+        return true; 
     } else if (pkt->senderState) {
-        if (recvSnoops) {
-            if (pkt->isRequest()) {
-                return true;
-            }
-        }
-
         DmaReqState *state;
         backoffTime >>= 2;
 
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index 1c7e1694a..b87dfa704 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -33,6 +33,7 @@
 #include <string>
 
 #include "arch/vtophys.hh"
+#include "base/compiler.hh"
 #include "base/debug.hh"
 #include "base/inet.hh"
 #include "base/types.hh"
@@ -404,7 +405,7 @@ Device::read(PacketPtr pkt)
 
     prepareRead(cpu, index);
 
-    uint64_t value = 0;
+    uint64_t value M5_VAR_USED = 0;
     if (pkt->getSize() == 4) {
         uint32_t reg = regData32(raddr);
         pkt->set(reg);
@@ -916,6 +917,7 @@ Device::rxKick()
                 VirtualReg *vn = &virtualRegs[i];
                 bool busy = Regs::get_RxDone_Busy(vn->RxDone);
                 if (vn->rxIndex != end) {
+#ifndef NDEBUG
                     bool dirty = vn->rxPacketOffset > 0;
                     const char *status;
 
@@ -933,6 +935,7 @@ Device::rxKick()
                             i, status, vn->rxUnique,
                             rxFifo.countPacketsBefore(vn->rxIndex),
                             vn->rxIndex->slack);
+#endif
                 } else if (busy) {
                     DPRINTF(EthernetSM, "vnic %d unmapped (rxunique %d)\n",
                             i, vn->rxUnique);
diff --git a/src/dev/sparc/mm_disk.cc b/src/dev/sparc/mm_disk.cc
index 1921f6d96..0095d9f1d 100644
--- a/src/dev/sparc/mm_disk.cc
+++ b/src/dev/sparc/mm_disk.cc
@@ -56,7 +56,6 @@ MmDisk::read(PacketPtr pkt)
 {
     Addr accessAddr;
     off_t sector;
-    off_t bytes_read;
     uint16_t d16;
     uint32_t d32;
     uint64_t d64;
@@ -68,10 +67,16 @@ MmDisk::read(PacketPtr pkt)
 
     if (sector != curSector) {
         if (dirty) {
-            bytes_read = image->write(diskData, curSector);
-            assert(bytes_read == SectorSize);
+#ifndef NDEBUG
+            off_t bytes_written =
+#endif
+                image->write(diskData, curSector);
+            assert(bytes_written == SectorSize);
         }
-        bytes_read = image->read(diskData,  sector);
+#ifndef NDEBUG
+        off_t bytes_read =
+#endif
+            image->read(diskData, sector);
         assert(bytes_read == SectorSize);
         curSector = sector;
     }
@@ -109,7 +114,6 @@ MmDisk::write(PacketPtr pkt)
 {
     Addr accessAddr;
     off_t sector;
-    off_t bytes_read;
     uint16_t d16;
     uint32_t d32;
     uint64_t d64;
@@ -121,10 +125,16 @@ MmDisk::write(PacketPtr pkt)
 
     if (sector != curSector) {
         if (dirty) {
-            bytes_read = image->write(diskData, curSector);
-            assert(bytes_read == SectorSize);
+#ifndef NDEBUG
+            off_t bytes_written =
+#endif
+                image->write(diskData, curSector);
+            assert(bytes_written == SectorSize);
         }
-        bytes_read = image->read(diskData,  sector);
+#ifndef NDEBUG
+        off_t bytes_read =
+#endif
+            image->read(diskData,  sector);
         assert(bytes_read == SectorSize);
         curSector = sector;
     }
@@ -164,9 +174,11 @@ MmDisk::serialize(std::ostream &os)
 {
     // just write any dirty changes to the cow layer it will take care of
     // serialization
-    int bytes_read;
     if (dirty) {
-        bytes_read = image->write(diskData, curSector);
+#ifndef NDEBUG
+        int bytes_read =
+#endif
+            image->write(diskData, curSector);
         assert(bytes_read == SectorSize);
     }
 }
diff --git a/src/dev/terminal.cc b/src/dev/terminal.cc
index 74d5ddde7..a11d45554 100644
--- a/src/dev/terminal.cc
+++ b/src/dev/terminal.cc
@@ -259,17 +259,13 @@ Terminal::write(const uint8_t *buf, size_t len)
 uint8_t
 Terminal::in()
 {
-    bool empty;
     uint8_t c;
 
-    empty = rxbuf.empty();
-    assert(!empty);
+    assert(!rxbuf.empty());
     rxbuf.read((char *)&c, 1);
-    empty = rxbuf.empty();
-
 
     DPRINTF(TerminalVerbose, "in: \'%c\' %#02x more: %d\n",
-            isprint(c) ? c : ' ', c, !empty);
+            isprint(c) ? c : ' ', c, !rxbuf.empty());
 
     return c;
 }
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 0ec2dbc07..f47e73c74 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -93,9 +93,7 @@ PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
             new_vaddr, size);
 
     for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
-        PTableItr iter = pTable.find(vaddr);
-
-        assert(iter != pTable.end());
+        assert(pTable.find(vaddr) != pTable.end());
 
         pTable[new_vaddr] = pTable[vaddr];
         pTable.erase(vaddr);
@@ -112,9 +110,7 @@ PageTable::unmap(Addr vaddr, int64_t size)
     DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
 
     for (; size > 0; size -= pageSize, vaddr += pageSize) {
-        PTableItr iter = pTable.find(vaddr);
-
-        assert(iter != pTable.end());
+        assert(pTable.find(vaddr) != pTable.end());
 
         pTable.erase(vaddr);
     }
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index 2d8ae4ca8..16c5bc5a1 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -913,7 +913,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   transition(SS, {L1_GETS, L1_GET_INSTR}) {
     ds_sendSharedDataToRequestor;
     nn_addSharer;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
@@ -923,7 +922,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     d_sendDataToRequestor;
     // fw_sendFwdInvToSharers;
     fwm_sendFwdInvToSharersMinusRequestor;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
@@ -931,7 +929,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   transition(SS, L1_UPGRADE, SS_MB) {
     fwm_sendFwdInvToSharersMinusRequestor;
     ts_sendInvAckToUpgrader;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
@@ -951,7 +948,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   transition(M, L1_GETX, MT_MB) {
     d_sendDataToRequestor;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
@@ -959,14 +955,12 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   transition(M, L1_GET_INSTR, SS) {
     d_sendDataToRequestor;
     nn_addSharer;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
 
   transition(M, L1_GETS, MT_MB) {
     dd_sendExclusiveDataToRequestor;
-    uu_profileMiss;
     set_setMRU;
     jj_popL1RequestQueue;
   }
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index 423272905..d026e7b90 100644
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -110,8 +110,16 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   void set_tbe(TBE tbe);
   void unset_tbe();
       
-  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, directory[addr]);
+  Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+    Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+    if (is_valid(dir_entry)) {
+      return dir_entry;
+    }
+
+    dir_entry :=  static_cast(Entry, "pointer",
+                              directory.allocate(addr, new Entry));
+    return dir_entry;
   }
 
   State getState(TBE tbe, Address addr) {
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index 2bd3afa44..40b919c92 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -79,8 +79,16 @@ machine(Directory, "Directory protocol")
   void set_tbe(TBE b);
   void unset_tbe();
 
-  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, directory[addr]);
+  Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+    Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+    if (is_valid(dir_entry)) {
+      return dir_entry;
+    }
+
+    dir_entry :=  static_cast(Entry, "pointer",
+                              directory.allocate(addr, new Entry));
+    return dir_entry;
   }
  
   State getState(TBE tbe, Address addr) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index b71518b3f..202bd11f6 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -126,8 +126,16 @@ machine(Directory, "Directory protocol")
   void set_tbe(TBE b);
   void unset_tbe();
 
-  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, directory[addr]);
+  Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+    Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+    if (is_valid(dir_entry)) {
+      return dir_entry;
+    }
+
+    dir_entry :=  static_cast(Entry, "pointer",
+                              directory.allocate(addr, new Entry));
+    return dir_entry;
   }
 
   State getState(TBE tbe, Address addr) {
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 9e6c6c99b..39e8a8d27 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -165,8 +165,16 @@ machine(Directory, "Token protocol")
   void set_tbe(TBE b);
   void unset_tbe();
 
-  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, directory[addr]);
+  Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+    Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+    if (is_valid(dir_entry)) {
+      return dir_entry;
+    }
+
+    dir_entry :=  static_cast(Entry, "pointer",
+                              directory.allocate(addr, new Entry));
+    return dir_entry;
   }
 
   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index a4f4bf17a..a20619d46 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -186,8 +186,16 @@ machine(Directory, "AMD Hammer-like protocol")
 
   TBETable TBEs, template_hack="<Directory_TBE>";
 
-  Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, directory[addr]);
+  Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+    Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+    if (is_valid(dir_entry)) {
+      return dir_entry;
+    }
+
+    dir_entry :=  static_cast(Entry, "pointer",
+                              directory.allocate(addr, new Entry));
+    return dir_entry;
   }
 
   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index cc404394d..c76e0fe3e 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -125,6 +125,7 @@ structure(AbstractEntry, primitive="yes", external = "yes") {
 }
 
 structure (DirectoryMemory, external = "yes") {
+  AbstractEntry allocate(Address, AbstractEntry);
   AbstractEntry lookup(Address);
   bool isPresent(Address);
   void invalidateBlock(Address);
diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh
index ea10b83f1..724c5d9e9 100644
--- a/src/mem/ruby/common/Set.hh
+++ b/src/mem/ruby/common/Set.hh
@@ -35,8 +35,20 @@
 #include <iostream>
 #include <limits>
 
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/system/System.hh"
+#include "mem/ruby/common/TypeDefines.hh"
+
+/*
+ * This defines the number of longs (32-bits on 32 bit machines,
+ * 64-bit on 64-bit AMD machines) to use to hold the set...
+ * the default is 4, allowing 128 or 256 different members
+ * of the set.
+ *
+ * This should never need to be changed for correctness reasons,
+ * though increasing it will increase performance for larger
+ * set sizes at the cost of a (much) larger memory footprint
+ *
+ */
+const int NUMBER_WORDS_PER_SET = 1;
 
 class Set
 {
diff --git a/src/mem/ruby/eventqueue/RubyEventQueue.cc b/src/mem/ruby/eventqueue/RubyEventQueue.cc
index 0e5a68e39..4ea530b05 100644
--- a/src/mem/ruby/eventqueue/RubyEventQueue.cc
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.cc
@@ -31,7 +31,6 @@
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/eventqueue/RubyEventQueueNode.hh"
-#include "mem/ruby/system/System.hh"
 
 RubyEventQueue::RubyEventQueue(EventQueue* eventq, Tick _clock)
   : EventManager(eventq), m_clock(_clock)
diff --git a/src/mem/ruby/network/Network.cc b/src/mem/ruby/network/Network.cc
index adb90eba9..2aa120cdf 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -30,6 +30,7 @@
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/network/Topology.hh"
+#include "mem/ruby/system/System.hh"
 
 Network::Network(const Params *p)
     : SimObject(p)
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 157849149..08ad95017 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -46,8 +46,7 @@
 
 #include "mem/protocol/LinkDirection.hh"
 #include "mem/protocol/MessageSizeType.hh"
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/system/System.hh"
+#include "mem/ruby/common/TypeDefines.hh"
 #include "params/RubyNetwork.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/mem/ruby/network/Topology.cc b/src/mem/ruby/network/Topology.cc
index a342d6d02..201919850 100644
--- a/src/mem/ruby/network/Topology.cc
+++ b/src/mem/ruby/network/Topology.cc
@@ -37,7 +37,6 @@
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/network/Topology.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
-#include "mem/ruby/system/System.hh"
 
 using namespace std;
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
index fccd73ee2..aee05b696 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
@@ -30,6 +30,7 @@
 
 #include <cassert>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
index 4adc8d98c..628c47dda 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
@@ -31,6 +31,7 @@
 #include <cassert>
 #include <cmath>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
index 829642bb9..8a83fcca2 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
@@ -28,6 +28,7 @@
  * Authors: Niket Agarwal
  */
 
+#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh"
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
index 7c7a7d428..35a9f06e1 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
@@ -28,6 +28,7 @@
  * Authors: Niket Agarwal
  */
 
+#include "base/cast.hh"
 #include "mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh"
 #include "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
 #include "mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh"
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
index 2c0d9f3aa..4fc2662ba 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
@@ -30,6 +30,7 @@
 
 #include <cassert>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
index a41c2768d..b38e2b1d6 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
@@ -31,6 +31,7 @@
 #include <cassert>
 #include <cmath>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
index 9965d3211..205a43138 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
@@ -28,6 +28,7 @@
  * Authors: Niket Agarwal
  */
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/network/garnet/flexible-pipeline/InVcState.hh"
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc
index f8b08d551..885e93796 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -28,6 +28,7 @@
 
 #include <algorithm>
 
+#include "base/cast.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/network/simple/PerfectSwitch.hh"
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 645d1b4f1..0eb8887d2 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -29,6 +29,7 @@
 #include <cassert>
 #include <numeric>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "mem/protocol/TopologyType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
index a678a657d..d9dadbd00 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -28,6 +28,7 @@
 
 #include <numeric>
 
+#include "base/cast.hh"
 #include "base/stl_helpers.hh"
 #include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc
index b248c6c6c..80697cb58 100644
--- a/src/mem/ruby/network/simple/Throttle.cc
+++ b/src/mem/ruby/network/simple/Throttle.cc
@@ -28,6 +28,7 @@
 
 #include <cassert>
 
+#include "base/cast.hh"
 #include "base/cprintf.hh"
 #include "debug/RubyNetwork.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index a26fa044e..04bbb87d8 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -27,6 +27,7 @@
  */
 
 #include "mem/ruby/slicc_interface/AbstractController.hh"
+#include "mem/ruby/system/System.hh"
 
 AbstractController::AbstractController(const Params *p) : SimObject(p)
 {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 1eefa4fba..ca37a90de 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -51,15 +51,11 @@ class AbstractController : public SimObject, public Consumer
     typedef RubyControllerParams Params;
     AbstractController(const Params *p);
     const Params *params() const { return (const Params *)_params; }
-
-    // returns the number of controllers created of the specific subtype
-    //  virtual int getNumberOfControllers() const = 0;
     virtual MessageBuffer* getMandatoryQueue() const = 0;
     virtual const int & getVersion() const = 0;
     virtual const std::string toString() const = 0;  // returns text version of
                                                      // controller type
     virtual const std::string getName() const = 0;   // return instance name
-    virtual const MachineType getMachineType() const = 0;
     virtual void blockOnQueue(Address, MessageBuffer*) = 0;
     virtual void unblock(Address) = 0;
     virtual void initNetworkPtr(Network* net_ptr) = 0;
diff --git a/src/mem/ruby/slicc_interface/AbstractEntry.hh b/src/mem/ruby/slicc_interface/AbstractEntry.hh
index fb1af2ea0..b10306281 100644
--- a/src/mem/ruby/slicc_interface/AbstractEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractEntry.hh
@@ -32,8 +32,6 @@
 #include <iostream>
 
 #include "mem/protocol/AccessPermission.hh"
-#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
 
 class DataBlock;
 
diff --git a/src/mem/ruby/system/AbstractReplacementPolicy.hh b/src/mem/ruby/system/AbstractReplacementPolicy.hh
index 3ddf4ab60..d03685c65 100644
--- a/src/mem/ruby/system/AbstractReplacementPolicy.hh
+++ b/src/mem/ruby/system/AbstractReplacementPolicy.hh
@@ -29,7 +29,7 @@
 #ifndef __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
 #define __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
 
-#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/common/TypeDefines.hh"
 
 class AbstractReplacementPolicy
 {
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index ab3ec4b29..79ab9b070 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -39,3 +39,4 @@ class RubyCache(SimObject):
     assoc = Param.Int("");
     replacement_policy = Param.String("PSEUDO_LRU", "");
     start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
+    is_icache = Param.Bool(False, "is instruction only cache");
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index fbf303ed8..1564128d3 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p)
     m_policy = p->replacement_policy;
     m_profiler_ptr = new CacheProfiler(name());
     m_start_index_bit = p->start_index_bit;
+    m_is_instruction_only_cache = p->is_icache;
 }
 
 void
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 0e82ba3eb..763eb586a 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -30,7 +30,6 @@
 #include "mem/protocol/SequencerMsg.hh"
 #include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
-#include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/ruby/system/DMASequencer.hh"
 #include "mem/ruby/system/System.hh"
 
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index a91f05a69..03aa68919 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -59,7 +59,7 @@ DirectoryMemory::init()
     if (m_use_map) {
         m_sparseMemory = new SparseMemory(m_map_levels);
     } else {
-        m_entries = new Directory_Entry*[m_num_entries];
+        m_entries = new AbstractEntry*[m_num_entries];
         for (int i = 0; i < m_num_entries; i++)
             m_entries[i] = NULL;
         m_ram = g_system_ptr->getMemoryVector();
@@ -150,38 +150,40 @@ DirectoryMemory::mapAddressToLocalIdx(PhysAddress address)
     return ret >> (RubySystem::getBlockSizeBits());
 }
 
-Directory_Entry&
+AbstractEntry*
 DirectoryMemory::lookup(PhysAddress address)
 {
     assert(isPresent(address));
-    Directory_Entry* entry;
+    DPRINTF(RubyCache, "Looking up address: %s\n", address);
+
+    if (m_use_map) {
+        return m_sparseMemory->lookup(address);
+    } else {
+        uint64_t idx = mapAddressToLocalIdx(address);
+        assert(idx < m_num_entries);
+        return m_entries[idx];
+    }
+}
+
+AbstractEntry*
+DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry)
+{
+    assert(isPresent(address));
     uint64 idx;
     DPRINTF(RubyCache, "Looking up address: %s\n", address);
 
     if (m_use_map) {
-        if (m_sparseMemory->exist(address)) {
-            entry = m_sparseMemory->lookup(address);
-            assert(entry != NULL);
-        } else {
-            // Note: SparseMemory internally creates a new Directory Entry
-            m_sparseMemory->add(address);
-            entry = m_sparseMemory->lookup(address);
-            entry->changePermission(AccessPermission_Read_Write);
-        }
+        m_sparseMemory->add(address, entry);
+        entry->changePermission(AccessPermission_Read_Write);
     } else {
         idx = mapAddressToLocalIdx(address);
         assert(idx < m_num_entries);
-        entry = m_entries[idx];
-
-        if (entry == NULL) {
-            entry = new Directory_Entry();
-            entry->getDataBlk().assign(m_ram->getBlockPtr(address));
-            entry->changePermission(AccessPermission_Read_Only);
-            m_entries[idx] = entry;
-        }
+        entry->getDataBlk().assign(m_ram->getBlockPtr(address));
+        entry->changePermission(AccessPermission_Read_Only);
+        m_entries[idx] = entry;
     }
 
-    return *entry;
+    return entry;
 }
 
 void
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 79b04726a..1b4d09b8e 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -32,9 +32,8 @@
 #include <iostream>
 #include <string>
 
-#include "mem/protocol/Directory_Entry.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/slicc_interface/AbstractEntry.hh"
 #include "mem/ruby/system/MemoryVector.hh"
 #include "mem/ruby/system/SparseMemory.hh"
 #include "params/RubyDirectoryMemory.hh"
@@ -58,7 +57,9 @@ class DirectoryMemory : public SimObject
     void printConfig(std::ostream& out) const;
     static void printGlobalConfig(std::ostream & out);
     bool isPresent(PhysAddress address);
-    Directory_Entry& lookup(PhysAddress address);
+    AbstractEntry* lookup(PhysAddress address);
+    AbstractEntry* allocate(const PhysAddress& address,
+                            AbstractEntry* new_entry);
 
     void invalidateBlock(PhysAddress address);
 
@@ -72,7 +73,7 @@ class DirectoryMemory : public SimObject
 
   private:
     const std::string m_name;
-    Directory_Entry **m_entries;
+    AbstractEntry **m_entries;
     // int m_size;  // # of memory module blocks this directory is
                     // responsible for
     uint64 m_size_bytes;
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index eb27c0f78..2ab0736e5 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -104,8 +104,8 @@
  *
  */
 
+#include "base/cast.hh"
 #include "base/cprintf.hh"
-#include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/network/Network.hh"
@@ -113,7 +113,6 @@
 #include "mem/ruby/slicc_interface/NetworkMessage.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/system/MemoryControl.hh"
-#include "mem/ruby/system/System.hh"
 
 using namespace std;
 
diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh
index 2b3cca603..1534851d5 100644
--- a/src/mem/ruby/system/MemoryControl.hh
+++ b/src/mem/ruby/system/MemoryControl.hh
@@ -34,14 +34,11 @@
 #include <string>
 
 #include "mem/protocol/MemoryMsg.hh"
-#include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
-#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/profiler/MemCntrlProfiler.hh"
 #include "mem/ruby/slicc_interface/Message.hh"
 #include "mem/ruby/system/AbstractMemOrCache.hh"
 #include "mem/ruby/system/MemoryNode.hh"
-#include "mem/ruby/system/System.hh"
 #include "params/RubyMemoryControl.hh"
 #include "sim/sim_object.hh"
 
diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh
index d2f58b0db..a57b3ec76 100644
--- a/src/mem/ruby/system/PersistentTable.hh
+++ b/src/mem/ruby/system/PersistentTable.hh
@@ -34,7 +34,6 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/AccessType.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/system/MachineID.hh"
 
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript
index 4cf0b31ad..66d7d95bb 100644
--- a/src/mem/ruby/system/SConscript
+++ b/src/mem/ruby/system/SConscript
@@ -49,6 +49,6 @@ Source('WireBuffer.cc')
 Source('MemoryNode.cc')
 Source('PersistentTable.cc')
 Source('RubyPort.cc')
-Source('Sequencer.cc', Werror=False)
+Source('Sequencer.cc')
 Source('System.cc')
 Source('TimerTable.cc')
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 9010178be..7137dcc28 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -221,10 +221,8 @@ Sequencer::printConfig(ostream& out) const
 RequestStatus
 Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
 {
-    int total_outstanding =
-        m_writeRequestTable.size() + m_readRequestTable.size();
-
-    assert(m_outstanding_count == total_outstanding);
+    assert(m_outstanding_count ==
+        (m_writeRequestTable.size() + m_readRequestTable.size()));
 
     // See if we should schedule a deadlock check
     if (deadlockCheckEvent.scheduled() == false) {
@@ -285,8 +283,8 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
     }
 
     g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
-    total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
-    assert(m_outstanding_count == total_outstanding);
+    assert(m_outstanding_count ==
+        (m_writeRequestTable.size() + m_readRequestTable.size()));
 
     return RequestStatus_Ready;
 }
diff --git a/src/mem/ruby/system/SparseMemory.cc b/src/mem/ruby/system/SparseMemory.cc
index fd90e2214..8e4f37c46 100644
--- a/src/mem/ruby/system/SparseMemory.cc
+++ b/src/mem/ruby/system/SparseMemory.cc
@@ -92,9 +92,7 @@ SparseMemory::recursivelyRemoveTables(SparseMapType* curTable, int curLevel)
             delete nextTable;
         } else {
             // If at the last level, delete the directory entry
-            Directory_Entry* dirEntry;
-            dirEntry = (Directory_Entry*)(entryStruct->entry);
-            delete dirEntry;
+            delete (AbstractEntry*)(entryStruct->entry);
         }
         entryStruct->entry = NULL;
     }
@@ -149,7 +147,7 @@ SparseMemory::exist(const Address& address) const
 
 // add an address to memory
 void
-SparseMemory::add(const Address& address)
+SparseMemory::add(const Address& address, AbstractEntry* entry)
 {
     assert(address == line_address(address));
     assert(!exist(address));
@@ -187,9 +185,8 @@ SparseMemory::add(const Address& address)
 
             // if the last level, add a directory entry.  Otherwise add a map.
             if (level == (m_number_of_levels - 1)) {
-                Directory_Entry* tempDirEntry = new Directory_Entry();
-                tempDirEntry->getDataBlk().clear();
-                newEntry = (void*)tempDirEntry;
+                entry->getDataBlk().clear();
+                newEntry = (void*)entry;
             } else {
                 SparseMapType* tempMap = new SparseMapType;
                 newEntry = (void*)(tempMap);
@@ -262,10 +259,8 @@ SparseMemory::recursivelyRemoveLevels(const Address& address,
         // if this is the last level, we have reached the Directory
         // Entry and thus we should delete it including the
         // SparseMemEntry container struct.
-        Directory_Entry* dirEntry;
-        dirEntry = (Directory_Entry*)(entryStruct->entry);
+        delete (AbstractEntry*)(entryStruct->entry);
         entryStruct->entry = NULL;
-        delete dirEntry;
         curInfo.curTable->erase(curAddress);
         m_removes_per_level[curInfo.level]++;
     }
@@ -303,17 +298,14 @@ SparseMemory::remove(const Address& address)
 }
 
 // looks an address up in memory
-Directory_Entry*
+AbstractEntry*
 SparseMemory::lookup(const Address& address)
 {
-    assert(exist(address));
     assert(address == line_address(address));
 
-    DPRINTF(RubyCache, "address: %s\n", address);
-
     Address curAddress;
     SparseMapType* curTable = m_map_head;
-    Directory_Entry* entry = NULL;
+    AbstractEntry* entry = NULL;
 
     // Initiallize the high bit to be the total number of bits plus
     // the block offset.  However the highest bit index is one less
@@ -336,13 +328,18 @@ SparseMemory::lookup(const Address& address)
         // Adjust the highBit value for the next level
         highBit -= m_number_of_bits_per_level[level];
 
-        // The entry should be in the table and valid
-        curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
-        assert(curTable != NULL);
+        // If the address is found, move on to the next level.
+        // Otherwise, return not found
+        if (curTable->count(curAddress) != 0) {
+            curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
+        } else {
+            DPRINTF(RubyCache, "Not found\n");
+            return NULL;
+        }
     }
 
     // The last entry actually points to the Directory entry not a table
-    entry = (Directory_Entry*)curTable;
+    entry = (AbstractEntry*)curTable;
 
     return entry;
 }
diff --git a/src/mem/ruby/system/SparseMemory.hh b/src/mem/ruby/system/SparseMemory.hh
index 78a3080a1..f6937ef54 100644
--- a/src/mem/ruby/system/SparseMemory.hh
+++ b/src/mem/ruby/system/SparseMemory.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 
 #include "base/hashmap.hh"
-#include "mem/protocol/Directory_Entry.hh"
+#include "mem/ruby/slicc_interface/AbstractEntry.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
 
@@ -60,10 +60,10 @@ class SparseMemory
     void printConfig(std::ostream& out) { }
 
     bool exist(const Address& address) const;
-    void add(const Address& address);
+    void add(const Address& address, AbstractEntry*);
     void remove(const Address& address);
 
-    Directory_Entry* lookup(const Address& address);
+    AbstractEntry* lookup(const Address& address);
 
     // Print cache contents
     void print(std::ostream& out) const;
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index 15abf1c0f..704cc3b27 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -50,19 +50,6 @@ class Network;
 class Profiler;
 class Tracer;
 
-/*
- * This defines the number of longs (32-bits on 32 bit machines,
- * 64-bit on 64-bit AMD machines) to use to hold the set...
- * the default is 4, allowing 128 or 256 different members
- * of the set.
- *
- * This should never need to be changed for correctness reasons,
- * though increasing it will increase performance for larger
- * set sizes at the cost of a (much) larger memory footprint
- *
- */
-const int NUMBER_WORDS_PER_SET = 1;
-
 class RubySystem : public SimObject
 {
   public:
diff --git a/src/mem/slicc/ast/FormalParamAST.py b/src/mem/slicc/ast/FormalParamAST.py
index e94f24ccb..6ed5bca0a 100644
--- a/src/mem/slicc/ast/FormalParamAST.py
+++ b/src/mem/slicc/ast/FormalParamAST.py
@@ -52,8 +52,9 @@ class FormalParamAST(AST):
                 self.pairs)
         self.symtab.newSymbol(v)
         if self.pointer or str(type) == "TBE" or (
-           "interface" in type and type["interface"] == "AbstractCacheEntry"):
-
+           "interface" in type and (
+               type["interface"] == "AbstractCacheEntry" or
+               type["interface"] == "AbstractEntry")):
             return type, "%s* %s" % (type.c_ident, param)
         else:
             return type, "const %s& %s" % (type.c_ident, param)
diff --git a/src/mem/slicc/ast/LocalVariableAST.py b/src/mem/slicc/ast/LocalVariableAST.py
index b779415f3..0b77323b7 100644
--- a/src/mem/slicc/ast/LocalVariableAST.py
+++ b/src/mem/slicc/ast/LocalVariableAST.py
@@ -52,7 +52,9 @@ class LocalVariableAST(StatementAST):
                 self.pairs)
         self.symtab.newSymbol(v)
         if self.pointer or str(type) == "TBE" or (
-           "interface" in type and type["interface"] == "AbstractCacheEntry"):
+           "interface" in type and (
+               type["interface"] == "AbstractCacheEntry" or
+               type["interface"] == "AbstractEntry")):
             code += "%s* %s" % (type.c_ident, ident)
         else:
             code += "%s %s" % (type.c_ident, ident)
diff --git a/src/mem/slicc/ast/MemberExprAST.py b/src/mem/slicc/ast/MemberExprAST.py
index 412c178d8..6a6fc49bb 100644
--- a/src/mem/slicc/ast/MemberExprAST.py
+++ b/src/mem/slicc/ast/MemberExprAST.py
@@ -41,7 +41,10 @@ class MemberExprAST(ExprAST):
         return_type, gcode = self.expr_ast.inline(True)
         fix = code.nofix()
 
-        if str(return_type) == "TBE" or ("interface" in return_type and return_type["interface"] == "AbstractCacheEntry"):
+        if str(return_type) == "TBE" \
+           or ("interface" in return_type and
+            (return_type["interface"] == "AbstractCacheEntry" or
+             return_type["interface"] == "AbstractEntry")):
             code("(*$gcode).m_${{self.field}}")
         else:
             code("($gcode).m_${{self.field}}")
diff --git a/src/mem/slicc/ast/MethodCallExprAST.py b/src/mem/slicc/ast/MethodCallExprAST.py
index cfee9b19d..cf30cfa96 100644
--- a/src/mem/slicc/ast/MethodCallExprAST.py
+++ b/src/mem/slicc/ast/MethodCallExprAST.py
@@ -162,8 +162,10 @@ class MemberMethodCallExprAST(MethodCallExprAST):
             prefix = "static_cast<%s &>" % return_type.c_ident
 
         if str(obj_type) == "AbstractCacheEntry" or \
-           ("interface" in obj_type and
-            obj_type["interface"] == "AbstractCacheEntry"):
+           str(obj_type) == "AbstractEntry" or \
+           ("interface" in obj_type and (
+            obj_type["interface"] == "AbstractCacheEntry" or
+            obj_type["interface"] == "AbstractEntry")):
             prefix = "%s((*(%s))." % (prefix, code)
         else:
             prefix = "%s((%s)." % (prefix, code)
diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py
index cc3091c8a..a9816bd3d 100644
--- a/src/mem/slicc/ast/PeekStatementAST.py
+++ b/src/mem/slicc/ast/PeekStatementAST.py
@@ -60,7 +60,7 @@ class PeekStatementAST(StatementAST):
         code('''
 {
     // Declare message
-    const $mtid* in_msg_ptr;
+    const $mtid* in_msg_ptr M5_VAR_USED;
     in_msg_ptr = dynamic_cast<const $mtid *>(($qcode).${{self.method}}());
     assert(in_msg_ptr != NULL); // Check the cast result
 ''')
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 4d3618093..a3ea1ca8a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -253,7 +253,6 @@ public:
     const int & getVersion() const;
     const std::string toString() const;
     const std::string getName() const;
-    const MachineType getMachineType() const;
     void stallBuffer(MessageBuffer* buf, Address addr);
     void wakeUpBuffers(Address addr);
     void wakeUpAllBuffers();
@@ -411,6 +410,7 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
 #include <sstream>
 #include <string>
 
+#include "base/compiler.hh"
 #include "base/cprintf.hh"
 #include "debug/RubyGenerated.hh"
 #include "debug/RubySlicc.hh"
@@ -705,12 +705,6 @@ $c_ident::getName() const
     return m_name;
 }
 
-const MachineType
-$c_ident::getMachineType() const
-{
-    return MachineType_${ident};
-}
-
 void
 $c_ident::stallBuffer(MessageBuffer* buf, Address addr)
 {
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 78524fe51..b389efcf2 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -373,6 +373,14 @@ EventQueue::debugVerify() const
     return true;
 }
 
+Event*
+EventQueue::replaceHead(Event* s)
+{
+    Event* t = head;
+    head = s;
+    return t;
+}
+
 void
 dumpMainQueue()
 {
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 1509d05a5..6dc25e760 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -408,6 +408,16 @@ class EventQueue : public Serializable
 
     bool debugVerify() const;
 
+    /**
+     *  function for replacing the head of the event queue, so that a
+     *  different set of events can run without disturbing events that have
+     *  already been scheduled. Already scheduled events can be processed
+     *  by replacing the original head back.
+     *  USING THIS FUNCTION CAN BE DANGEROUS TO THE HEALTH OF THE SIMULATOR.
+     *  NOT RECOMMENDED FOR USE.
+     */
+    Event* replaceHead(Event* s);
+
 #ifndef SWIG
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);