summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMitch Hayenga <mitch.hayenga@arm.com>2014-09-03 07:42:38 -0400
committerMitch Hayenga <mitch.hayenga@arm.com>2014-09-03 07:42:38 -0400
commit283935a6f0a17afe4574cc3c50c043515c866dfa (patch)
treea0646dcba419a9aa1b790d765a6d156db16f9839 /src
parent4f26bedc1883da58d1dceba2bbc555417b7a0cca (diff)
downloadgem5-283935a6f0a17afe4574cc3c50c043515c866dfa.tar.xz
cpu: Fix o3 quiesce fetch bug
O3 is supposed to stop fetching instructions once a quiesce is encountered. However due to a bug, it would continue fetching instructions from the current fetch buffer. This is because of a break statment that only broke out of the first of 2 nested loops. It should have broken out of both.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/fetch_impl.hh8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d583ae7b6..e20d2970a 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1236,6 +1236,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// ended this fetch block.
bool predictedBranch = false;
+ // Need to halt fetch if quiesce instruction detected
+ bool quiesce = false;
+
TheISA::MachInst *cacheInsts =
reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
@@ -1246,7 +1249,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Keep issuing while fetchWidth is available and branch is not
// predicted taken
while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
- && !predictedBranch) {
+ && !predictedBranch && !quiesce) {
// We need to process more memory if we aren't going to get a
// StaticInst from the rom, the current macroop, or what's already
// in the decoder.
@@ -1363,9 +1366,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
if (instruction->isQuiesce()) {
DPRINTF(Fetch,
- "Quiesce instruction encountered, halting fetch!");
+ "Quiesce instruction encountered, halting fetch!\n");
fetchStatus[tid] = QuiescePending;
status_change = true;
+ quiesce = true;
break;
}
} while ((curMacroop || decoder[tid]->instReady()) &&