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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 3ad31f61c27b505b299295008b8f52b44ddbd499 (patch) | |
| tree | 5c1911eca3706347e72578fbb3eb692ff1d0f754 /src | |
| parent | 54ab07e636a0e83527a87c5d88406e3b443b2e99 (diff) | |
| download | gem5-3ad31f61c27b505b299295008b8f52b44ddbd499.tar.xz | |
ARM: Decode the strex instructions.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 5d389458c..8f2dacade 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -229,19 +229,19 @@ def format ArmSyncMem() {{ case 0x14: return new Swpb(machInst, rt, rt2, rn); case 0x18: - return new WarnUnimplemented("strex", machInst); + return new %(strex)s(machInst, rt, rt2, rn, true, 0); case 0x19: return new %(ldrex)s(machInst, rt, rn, true, 0); case 0x1a: - return new WarnUnimplemented("strexd", machInst); + return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); case 0x1b: return new WarnUnimplemented("ldrexd", machInst); case 0x1c: - return new WarnUnimplemented("strexb", machInst); + return new %(strexb)s(machInst, rt, rt2, rn, true, 0); case 0x1d: return new %(ldrexb)s(machInst, rt, rn, true, 0); case 0x1e: - return new WarnUnimplemented("strexh", machInst); + return new %(strexh)s(machInst, rt, rt2, rn, true, 0); case 0x1f: return new %(ldrexh)s(machInst, rt, rn, true, 0); default: @@ -251,7 +251,11 @@ def format ArmSyncMem() {{ ''' % { "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), - "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2) + "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), + "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), + "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), + "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), + "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False) } }}; @@ -294,12 +298,13 @@ def format Thumb32LdrStrDExTbh() {{ const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); + const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); const uint32_t imm8 = bits(machInst, 7, 0); if (bits(op1, 1) == 0 && bits(op2, 1) == 0) { if (op1 == 0) { const uint32_t imm = bits(machInst, 7, 0) << 2; if (op2 == 0) { - return new WarnUnimplemented("strex", machInst); + return new %(strex)s(machInst, rt2, rt, rn, true, imm); } else { return new %(ldrex)s(machInst, rt, rn, true, imm); } @@ -307,11 +312,12 @@ def format Thumb32LdrStrDExTbh() {{ if (op2 == 0) { switch (op3) { case 0x4: - return new WarnUnimplemented("strexb", machInst); + return new %(strexb)s(machInst, rd, rt, rn, true, 0); case 0x5: - return new WarnUnimplemented("strexh", machInst); + return new %(strexh)s(machInst, rd, rt, rn, true, 0); case 0x7: - return new WarnUnimplemented("strexd", machInst); + return new %(strexd)s(machInst, rd, rt, + rt2, rn, true, 0); default: return new Unknown(machInst); } @@ -378,6 +384,10 @@ def format Thumb32LdrStrDExTbh() {{ "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), + "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), + "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), + "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), + "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False), "ldrd_w" : loadDoubleImmClassName(True, False, True), "ldrd_uw" : loadDoubleImmClassName(True, True, True), "ldrd_p" : loadDoubleImmClassName(False, False, False), |