ruby: restrict Address to being a type and not a variable name

Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

25 files changed, 735 insertions, 735 deletions

diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index 5d7e2bcfb..48845fdc6 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -125,7 +125,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   // TBE fields
   structure(TBE, desc="...") {
-    Address Address,              desc="Physical address for this TBE";
+    Address Addr,              desc="Physical address for this TBE";
     State TBEState,        desc="Transient state";
     DataBlock DataBlk,                desc="Buffer for the data block";
     bool Dirty, default="false",   desc="data is dirty";
@@ -348,36 +348,36 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   // Response IntraChip L1 Network - response msg to this L1 cache
   in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {
     if (responseIntraChipL1Network_in.isReady()) {
-      peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
+      peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L1_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L1_TBEs[in_msg.Addr];
 
         if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
         } else if(in_msg.Type == CoherenceResponseType:DATA) {
-          if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
-               getState(tbe, cache_entry, in_msg.Address) == State:IS_I ||
-               getState(tbe, cache_entry, in_msg.Address) == State:PF_IS ||
-               getState(tbe, cache_entry, in_msg.Address) == State:PF_IS_I) &&
+          if ((getState(tbe, cache_entry, in_msg.Addr) == State:IS ||
+               getState(tbe, cache_entry, in_msg.Addr) == State:IS_I ||
+               getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS ||
+               getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS_I) &&
               machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
 
-              trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
+              trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
 
           } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
-            trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
           } else {
-            trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
           }
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
           if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
-            trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
           } else {
-            trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
           }
         } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
-          trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
         } else {
           error("Invalid L1 response type");
         }
@@ -388,22 +388,22 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   // Request InterChip network - request from this L1 cache to the shared L2
   in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank = 1) {
     if(requestIntraChipL1Network_in.isReady()) {
-      peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
+      peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L1_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L1_TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:GETX ||
                    in_msg.Type == CoherenceRequestType:UPGRADE) {
           // upgrade transforms to GETX due to race
-          trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
-          trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
         } else {
           error("Invalid forwarded request type");
         }
@@ -495,7 +495,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(a_issueGETS, "a", desc="Issue GETS") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -513,7 +513,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     peek(optionalQueue_in, RubyRequest) {
       enqueue(requestIntraChipL1Network_out, RequestMsg,
               latency=l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -530,7 +530,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GET_INSTR;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -549,7 +549,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       peek(optionalQueue_in, RubyRequest) {
           enqueue(requestIntraChipL1Network_out, RequestMsg,
                   latency=l1_request_latency) {
-              out_msg.Address := address;
+              out_msg.Addr := address;
               out_msg.Type := CoherenceRequestType:GET_INSTR;
               out_msg.Requestor := machineID;
               out_msg.Destination.add(
@@ -568,7 +568,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(b_issueGETX, "b", desc="Issue GETX") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := machineID;
         DPRINTF(RubySlicc, "%s\n", machineID);
@@ -587,7 +587,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       peek(optionalQueue_in, RubyRequest) {
           enqueue(requestIntraChipL1Network_out, RequestMsg,
                   latency=l1_request_latency) {
-              out_msg.Address := address;
+              out_msg.Addr := address;
               out_msg.Type := CoherenceRequestType:GETX;
               out_msg.Requestor := machineID;
               DPRINTF(RubySlicc, "%s\n", machineID);
@@ -609,7 +609,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(c_issueUPGRADE, "c", desc="Issue GETX") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:UPGRADE;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -627,7 +627,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     peek(requestIntraChipL1Network_in, RequestMsg) {
       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := cache_entry.DataBlk;
         out_msg.Dirty := cache_entry.Dirty;
@@ -641,7 +641,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.DataBlk := cache_entry.DataBlk;
       out_msg.Dirty := cache_entry.Dirty;
@@ -656,7 +656,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     peek(requestIntraChipL1Network_in, RequestMsg) {
       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := tbe.DataBlk;
         out_msg.Dirty := tbe.Dirty;
@@ -670,7 +670,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.DataBlk := tbe.DataBlk;
       out_msg.Dirty := tbe.Dirty;
@@ -684,7 +684,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
     peek(requestIntraChipL1Network_in, RequestMsg) {
       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -696,7 +696,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.DataBlk := cache_entry.DataBlk;
       out_msg.Dirty := cache_entry.Dirty;
@@ -710,7 +710,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
     enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.DataBlk := tbe.DataBlk;
       out_msg.Dirty := tbe.Dirty;
@@ -724,7 +724,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
     peek(requestIntraChipL1Network_in, RequestMsg) {
       enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -744,7 +744,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   action(g_issuePUTX, "g", desc="send data to the L2 cache") {
     enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.DataBlk := cache_entry.DataBlk;
       out_msg.Dirty := cache_entry.Dirty;
@@ -761,7 +761,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK;
       out_msg.Sender := machineID;
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -773,7 +773,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
       out_msg.Sender := machineID;
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index a11171990..e28abe336 100644
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -130,7 +130,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   // TBE fields
   structure(TBE, desc="...") {
-    Address Address,            desc="Physical address for this TBE";
+    Address Addr,            desc="Physical address for this TBE";
     State TBEState,             desc="Transient state";
     DataBlock DataBlk,          desc="Buffer for the data block";
     bool Dirty, default="false", desc="Data is Dirty";
@@ -289,17 +289,17 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
     if(L1unblockNetwork_in.isReady()) {
       peek(L1unblockNetwork_in,  ResponseMsg) {
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L2_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L2_TBEs[in_msg.Addr];
         DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
-                in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
+                in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
                 in_msg.Sender, in_msg.Type, in_msg.Destination);
 
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
-          trigger(Event:Exclusive_Unblock, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-          trigger(Event:Unblock, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
         } else {
           error("unknown unblock message");
         }
@@ -313,21 +313,21 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       peek(responseIntraChipL2Network_in, ResponseMsg) {
         // test wether it's from a local L1 or an off chip source
         assert(in_msg.Destination.isElement(machineID));
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L2_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L2_TBEs[in_msg.Addr];
 
         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
           if(in_msg.Type == CoherenceResponseType:DATA) {
             if (in_msg.Dirty) {
-              trigger(Event:WB_Data, in_msg.Address, cache_entry, tbe);
+              trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
             } else {
-              trigger(Event:WB_Data_clean, in_msg.Address, cache_entry, tbe);
+              trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
             }
           } else if (in_msg.Type == CoherenceResponseType:ACK) {
             if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
-              trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
+              trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
             } else {
-              trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+              trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
             }
           } else {
             error("unknown message type");
@@ -336,13 +336,13 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         } else { // external message
           if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
               // L2 now has data and all off-chip acks
-              trigger(Event:Mem_Data, in_msg.Address, cache_entry, tbe);
+              trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
           } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
               // L2 now has data and all off-chip acks
-              trigger(Event:Mem_Ack, in_msg.Address, cache_entry, tbe);
+              trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
           } else if(in_msg.Type == CoherenceResponseType:INV) {
               // L2 now has data and all off-chip acks
-              trigger(Event:MEM_Inv, in_msg.Address, cache_entry, tbe);
+              trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
           } else {
             error("unknown message type");
           }
@@ -355,11 +355,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
     if(L1RequestIntraChipL2Network_in.isReady()) {
       peek(L1RequestIntraChipL2Network_in,  RequestMsg) {
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L2_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L2_TBEs[in_msg.Addr];
 
         DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
-                in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
+                in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
                 in_msg.Requestor, in_msg.Type, in_msg.Destination);
 
         assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
@@ -367,24 +367,24 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
         if (is_valid(cache_entry)) {
           // The L2 contains the block, so proceeded with handling the request
-          trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
+          trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
                                                 in_msg.Requestor, cache_entry),
-                  in_msg.Address, cache_entry, tbe);
+                  in_msg.Addr, cache_entry, tbe);
         } else {
-          if (L2cache.cacheAvail(in_msg.Address)) {
+          if (L2cache.cacheAvail(in_msg.Addr)) {
             // L2 does't have the line, but we have space for it in the L2
-            trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
+            trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
                                                   in_msg.Requestor, cache_entry),
-                    in_msg.Address, cache_entry, tbe);
+                    in_msg.Addr, cache_entry, tbe);
           } else {
             // No room in the L2, so we need to make room before handling the request
-            Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Address));
+            Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
             if (isDirty(L2cache_entry)) {
-              trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Address),
-                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
+              trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
+                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
             } else {
-              trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Address),
-                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
+              trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
+                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
             }
           }
         }
@@ -398,7 +398,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
@@ -411,7 +411,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(cache_entry.Exclusive);
@@ -423,7 +423,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   action(c_exclusiveReplacement, "c", desc="Send data to memory") {
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -435,7 +435,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:ACK;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -446,7 +446,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:MEMORY_DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -460,7 +460,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -480,7 +480,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -500,7 +500,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -517,7 +517,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     assert(tbe.L1_GetS_IDs.count() > 0);
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
@@ -532,7 +532,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     assert(tbe.L1_GetS_IDs.count() == 1);
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.Destination := tbe.L1_GetS_IDs;  // internal nodes
@@ -546,7 +546,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
       assert(is_valid(tbe));
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.add(tbe.L1_GetX_ID);
@@ -554,7 +554,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       out_msg.DataBlk := cache_entry.DataBlk;
       out_msg.Dirty := cache_entry.Dirty;
       DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
-              out_msg.Address, out_msg.Destination, out_msg.DataBlk);
+              out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
   }
@@ -562,7 +562,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
     enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:INV;
       out_msg.Requestor := machineID;
       out_msg.Destination := cache_entry.Sharers;
@@ -574,7 +574,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination := cache_entry.Sharers;
@@ -587,7 +587,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination := cache_entry.Sharers;
@@ -695,7 +695,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   action(t_sendWBAck, "t", desc="Send writeback ACK") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:WB_ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -708,7 +708,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
       enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index 665e3461e..26a5c38df 100644
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -201,13 +201,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
       peek(requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (isGETRequest(in_msg.Type)) {
-          trigger(Event:Fetch, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Fetch, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:DMA_READ, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
-          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg);
           error("Invalid message");
@@ -221,9 +221,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
       peek(responseNetwork_in, ResponseMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
-          trigger(Event:Data, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Data, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:CleanReplacement, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:CleanReplacement, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -237,9 +237,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -253,7 +253,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(a_sendAck, "a", desc="Send ack to L2") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Sender);
@@ -265,7 +265,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(d_sendData, "d", desc="Send data to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -280,7 +280,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(aa_sendAck, "aa", desc="Send ack to L2") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -308,13 +308,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
         out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
 
         DPRINTF(RubySlicc, "%s\n", out_msg);
       }
@@ -324,7 +324,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Sender;
@@ -339,16 +339,16 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
     peek(responseNetwork_in, ResponseMsg) {
-      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
+      getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 //added by SS for dma
   action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := machineID;
@@ -366,7 +366,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := in_msg.DataBlk;   // we send the entire data block and rely on the dma controller to split it up if need be
         out_msg.Destination.add(map_Address_to_DMA(address));
@@ -377,14 +377,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
     peek(requestNetwork_in, RequestMsg) {
-      getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
+      getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
     }
   }
 
   action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
      peek(requestNetwork_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.OriginalRequestorMachId := machineID;
         //out_msg.DataBlk := in_msg.DataBlk;
@@ -401,7 +401,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Destination.add(map_Address_to_DMA(address));
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
@@ -428,7 +428,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:INV;
       out_msg.Sender := machineID;
       out_msg.Destination := getDirectoryEntry(address).Owner;
@@ -441,7 +441,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
   action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := in_msg.DataBlk;   // we send the entire data block and rely on the dma controller to split it up if need be
         out_msg.Destination.add(map_Address_to_DMA(address));
@@ -459,7 +459,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
       TBEs.allocate(address);
       set_tbe(TBEs[address]);
       tbe.DataBlk := in_msg.DataBlk;
-      tbe.PhysicalAddress := in_msg.Address;
+      tbe.PhysicalAddress := in_msg.Addr;
       tbe.Len := in_msg.Len;
     }
   }
@@ -477,7 +477,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.OriginalRequestorMachId := in_msg.Sender;
         //out_msg.DataBlk := in_msg.DataBlk;
diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index f377e13ee..8032c0bec 100644
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -94,9 +94,9 @@ machine(DMA, "DMA Controller")
     if (dmaResponseQueue_in.isReady()) {
       peek( dmaResponseQueue_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, makeLineAddress(in_msg.Address));
+          trigger(Event:Ack, makeLineAddress(in_msg.Addr));
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, makeLineAddress(in_msg.Address));
+          trigger(Event:Data, makeLineAddress(in_msg.Addr));
         } else {
           error("Invalid response type");
         }
@@ -107,7 +107,7 @@ machine(DMA, "DMA Controller")
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := in_msg.PhysicalAddress;
+        out_msg.Addr := in_msg.PhysicalAddress;
         out_msg.Type := CoherenceRequestType:DMA_READ;
         out_msg.DataBlk := in_msg.DataBlk;
         out_msg.Len := in_msg.Len;
@@ -120,7 +120,7 @@ machine(DMA, "DMA Controller")
   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-          out_msg.Address := in_msg.PhysicalAddress;
+          out_msg.Addr := in_msg.PhysicalAddress;
           out_msg.Type := CoherenceRequestType:DMA_WRITE;
           out_msg.DataBlk := in_msg.DataBlk;
           out_msg.Len := in_msg.Len;
diff --git a/src/mem/protocol/MESI_CMP_directory-msg.sm b/src/mem/protocol/MESI_CMP_directory-msg.sm
index 473012c61..85a54c1f2 100644
--- a/src/mem/protocol/MESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MESI_CMP_directory-msg.sm
@@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") {
 
 // RequestMsg
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,              desc="Physical address for this request";
+  Address Addr,              desc="Physical address for this request";
   CoherenceRequestType Type,    desc="Type of request (GetS, GetX, PutX, etc)";
   RubyAccessMode AccessMode,    desc="user/supervisor access type";
   MachineID Requestor      ,    desc="What component request";
@@ -72,7 +72,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   bool functionalRead(Packet *pkt) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:PUTX) {
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
 
     return false;
@@ -81,13 +81,13 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   bool functionalWrite(Packet *pkt) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
 // ResponseMsg
 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
-  Address Address,              desc="Physical address for this request";
+  Address Addr,              desc="Physical address for this request";
   CoherenceResponseType Type,   desc="Type of response (Ack, Data, etc)";
   MachineID Sender,             desc="What component sent the data";
   NetDest Destination,          desc="Node to whom the data is sent";
@@ -102,7 +102,7 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:MEMORY_DATA) {
 
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
 
     return false;
@@ -111,6 +111,6 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
   bool functionalWrite(Packet *pkt) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index a0a23c308..d22a0d3e9 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -195,22 +195,22 @@ machine(L1Cache, "MI Example L1 Cache")
 
   in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
     if (forwardRequestNetwork_in.isReady()) {
-      peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
+      peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") {
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
-          trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
-          trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
         }
         else {
           error("Unexpected message");
@@ -221,13 +221,13 @@ machine(L1Cache, "MI Example L1 Cache")
 
   in_port(responseNetwork_in, ResponseMsg, responseToCache) {
     if (responseNetwork_in.isReady()) {
-      peek(responseNetwork_in, ResponseMsg, block_on="Address") {
+      peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
         }
         else {
           error("Unexpected message");
@@ -261,7 +261,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
   action(a_issueRequest, "a", desc="Issue a request") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
-    out_msg.Address := address;
+    out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:GETX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -272,7 +272,7 @@ machine(L1Cache, "MI Example L1 Cache")
   action(b_issuePUT, "b", desc="Issue a PUT request") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -285,7 +285,7 @@ machine(L1Cache, "MI Example L1 Cache")
     peek(forwardRequestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -299,7 +299,7 @@ machine(L1Cache, "MI Example L1 Cache")
     peek(forwardRequestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index e1fd53594..389bc64b5 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -208,16 +208,16 @@ machine(Directory, "Directory protocol")
   in_port(requestQueue_in, RequestMsg, requestToDir) {
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
-        TBE tbe := TBEs[in_msg.Address];
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:GETS, in_msg.Address, tbe);
+          trigger(Event:GETS, in_msg.Addr, tbe);
         } else if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:GETX, in_msg.Address, tbe);
+          trigger(Event:GETX, in_msg.Addr, tbe);
         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
-          if (getDirectoryEntry(in_msg.Address).Owner.isElement(in_msg.Requestor)) {
-            trigger(Event:PUTX, in_msg.Address, tbe);
+          if (getDirectoryEntry(in_msg.Addr).Owner.isElement(in_msg.Requestor)) {
+            trigger(Event:PUTX, in_msg.Addr, tbe);
           } else {
-            trigger(Event:PUTX_NotOwner, in_msg.Address, tbe);
+            trigger(Event:PUTX_NotOwner, in_msg.Addr, tbe);
           }
         } else {
           error("Invalid message");
@@ -231,11 +231,11 @@ machine(Directory, "Directory protocol")
   in_port(memQueue_in, MemoryMsg, memBuffer) {
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
-        TBE tbe := TBEs[in_msg.Address];
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, tbe);
+          trigger(Event:Memory_Data, in_msg.Addr, tbe);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, tbe);
+          trigger(Event:Memory_Ack, in_msg.Addr, tbe);
         } else {
           DPRINTF(RubySlicc,"%s\n", in_msg.Type);
           error("Invalid message");
@@ -249,7 +249,7 @@ machine(Directory, "Directory protocol")
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -261,7 +261,7 @@ machine(Directory, "Directory protocol")
   action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := in_msg.OriginalRequestorMachId;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -273,7 +273,7 @@ machine(Directory, "Directory protocol")
   action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_NACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -289,7 +289,7 @@ machine(Directory, "Directory protocol")
   action(d_sendData, "d", desc="Send data to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -350,14 +350,14 @@ machine(Directory, "Directory protocol")
   action(f_forwardRequest, "f", desc="Forward request to owner") {
     peek(requestQueue_in, RequestMsg) {
       APPEND_TRANSITION_COMMENT("Own: ");
-      APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Address).Owner);
+      APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Addr).Owner);
       APPEND_TRANSITION_COMMENT("Req: ");
       APPEND_TRANSITION_COMMENT(in_msg.Requestor);
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
-        out_msg.Destination := getDirectoryEntry(in_msg.Address).Owner;
+        out_msg.Destination := getDirectoryEntry(in_msg.Addr).Owner;
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
       }
     }
@@ -366,7 +366,7 @@ machine(Directory, "Directory protocol")
   action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
         out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
@@ -387,8 +387,8 @@ machine(Directory, "Directory protocol")
     peek(requestQueue_in, RequestMsg) {
       // assert(in_msg.Dirty);
       // assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
-      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
-      //getDirectoryEntry(in_msg.Address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
+      getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
+      //getDirectoryEntry(in_msg.Addr).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
     }
   }
   
@@ -441,12 +441,12 @@ machine(Directory, "Directory protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         out_msg.MessageSize := in_msg.MessageSize;
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         DPRINTF(RubySlicc,"%s\n", out_msg);
       }
     }
@@ -455,7 +455,7 @@ machine(Directory, "Directory protocol")
   action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         //out_msg.OriginalRequestorMachId := machineID;
@@ -469,7 +469,7 @@ machine(Directory, "Directory protocol")
   action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
      peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         //out_msg.OriginalRequestorMachId := machineID;
         //out_msg.DataBlk := in_msg.DataBlk;
@@ -486,7 +486,7 @@ machine(Directory, "Directory protocol")
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
         // get incoming data
@@ -505,7 +505,7 @@ machine(Directory, "Directory protocol")
   action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm
index 0645371f6..568b79786 100644
--- a/src/mem/protocol/MI_example-msg.sm
+++ b/src/mem/protocol/MI_example-msg.sm
@@ -51,7 +51,7 @@ enumeration(CoherenceResponseType, desc="...") {
 
 // RequestMsg (and also forwarded requests)
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest Destination,             desc="Multicast destination mask";
@@ -61,7 +61,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   bool functionalRead(Packet *pkt) {
     // Valid data block is only present in PUTX messages
     if (Type == CoherenceRequestType:PUTX) {
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
     return false;
   }
@@ -69,13 +69,13 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   bool functionalWrite(Packet *pkt) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
 // ResponseMsg (and also unblock requests)
 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceResponseType Type,  desc="Type of response (Ack, Data, etc)";
   MachineID Sender,               desc="Node who sent the data";
   NetDest Destination,             desc="Node to whom the data is sent";
@@ -86,13 +86,13 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
   bool functionalRead(Packet *pkt) {
     // A check on message type should appear here so that only those
     // messages that contain data
-    return testAndRead(Address, DataBlk, pkt);
+    return testAndRead(Addr, DataBlk, pkt);
   }
 
   bool functionalWrite(Packet *pkt) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index c6acd43bf..5b09e220f 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -116,7 +116,7 @@ machine(L1Cache, "Directory protocol")
 
   // TBE fields
   structure(TBE, desc="...") {
-    Address Address,         desc="Physical address for this TBE";
+    Address Addr,         desc="Physical address for this TBE";
     State TBEState,          desc="Transient state";
     DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
     bool Dirty,              desc="Is the data dirty (different than memory)?";
@@ -263,8 +263,8 @@ machine(L1Cache, "Directory protocol")
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
         if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_acks, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:All_acks, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -277,36 +277,36 @@ machine(L1Cache, "Directory protocol")
   // Request Network
   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
     if (requestNetwork_in.isReady()) {
-      peek(requestNetwork_in, RequestMsg, block_on="Address") {
+      peek(requestNetwork_in, RequestMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
         DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type);
 
         if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
           if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) {
-            trigger(Event:Own_GETX, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:Own_GETX, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           } else {
-            trigger(Event:Fwd_GETX, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:Fwd_GETX, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:Fwd_GETS, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Fwd_GETS, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:Fwd_DMA, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Fwd_DMA, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
-          trigger(Event:Writeback_Ack, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Writeback_Ack, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) {
-          trigger(Event:Writeback_Ack_Data, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Writeback_Ack_Data, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
-          trigger(Event:Writeback_Nack, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Writeback_Nack, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Inv, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -317,16 +317,16 @@ machine(L1Cache, "Directory protocol")
   // Response Network
   in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
     if (responseToL1Cache_in.isReady()) {
-      peek(responseToL1Cache_in, ResponseMsg, block_on="Address") {
+      peek(responseToL1Cache_in, ResponseMsg, block_on="Addr") {
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Ack, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Data, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Exclusive_Data, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Exclusive_Data, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -415,7 +415,7 @@ machine(L1Cache, "Directory protocol")
   action(a_issueGETS, "a", desc="Issue GETS") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestNetwork_out, RequestMsg, latency= request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := MachineType:L1Cache;
@@ -431,7 +431,7 @@ machine(L1Cache, "Directory protocol")
   action(b_issueGETX, "b", desc="Issue GETX") {
     peek(mandatoryQueue_in, RubyRequest) {
       enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := MachineType:L1Cache;
@@ -447,7 +447,7 @@ machine(L1Cache, "Directory protocol")
   action(d_issuePUTX, "d", desc="Issue PUTX") {
     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L1Cache;
@@ -460,7 +460,7 @@ machine(L1Cache, "Directory protocol")
   action(dd_issuePUTO, "\d", desc="Issue PUTO") {
     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTO;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L1Cache;
@@ -473,7 +473,7 @@ machine(L1Cache, "Directory protocol")
   action(dd_issuePUTS, "\ds", desc="Issue PUTS") {
     // enqueue(writebackNetwork_out, RequestMsg, latency=request_latency) {
     enqueue(requestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTS;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L1Cache;
@@ -488,7 +488,7 @@ machine(L1Cache, "Directory protocol")
       assert(is_valid(cache_entry));
       if (in_msg.RequestorMachine == MachineType:L2Cache) {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -500,11 +500,11 @@ machine(L1Cache, "Directory protocol")
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:Response_Data;
         }
-        DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Address);
+        DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Addr);
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -523,7 +523,7 @@ machine(L1Cache, "Directory protocol")
   action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
       assert(is_valid(cache_entry));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L1Cache;
@@ -541,7 +541,7 @@ machine(L1Cache, "Directory protocol")
       assert(is_valid(cache_entry));
       if (in_msg.RequestorMachine == MachineType:L2Cache) {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -556,7 +556,7 @@ machine(L1Cache, "Directory protocol")
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -575,7 +575,7 @@ machine(L1Cache, "Directory protocol")
     peek(requestNetwork_in, RequestMsg) {
       if (in_msg.RequestorMachine == MachineType:L1Cache) {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:ACK;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -586,7 +586,7 @@ machine(L1Cache, "Directory protocol")
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:ACK;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -601,7 +601,7 @@ machine(L1Cache, "Directory protocol")
 
   action(g_sendUnblock, "g", desc="Send unblock to memory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L1Cache;
@@ -613,7 +613,7 @@ machine(L1Cache, "Directory protocol")
 
   action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L1Cache;
@@ -684,7 +684,7 @@ machine(L1Cache, "Directory protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS;
       }
     }
@@ -697,7 +697,7 @@ machine(L1Cache, "Directory protocol")
   action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DMA_ACK;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:L1Cache;
@@ -716,7 +716,7 @@ machine(L1Cache, "Directory protocol")
       if (in_msg.RequestorMachine == MachineType:L1Cache ||
           in_msg.RequestorMachine == MachineType:DMA) {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -730,7 +730,7 @@ machine(L1Cache, "Directory protocol")
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -751,7 +751,7 @@ machine(L1Cache, "Directory protocol")
       assert(is_valid(tbe));
       if (in_msg.RequestorMachine == MachineType:L1Cache) {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -764,7 +764,7 @@ machine(L1Cache, "Directory protocol")
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
           out_msg.Sender := machineID;
           out_msg.SenderMachine := MachineType:L1Cache;
@@ -783,7 +783,7 @@ machine(L1Cache, "Directory protocol")
   action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") {
     enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L1Cache;
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 475da1fbc..de776192d 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -187,7 +187,7 @@ machine(L2Cache, "Token protocol")
 
   // TBE fields
   structure(TBE, desc="...") {
-    Address address,                      desc="Physical address for this TBE";
+    Address Addr,                      desc="Physical address for this TBE";
     State TBEState,                       desc="Transient state";
     Address PC,                           desc="Program counter of request";
     DataBlock DataBlk,                    desc="Buffer for the data block";
@@ -540,8 +540,8 @@ machine(L2Cache, "Token protocol")
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
         if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_Acks, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:All_Acks, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -556,27 +556,27 @@ machine(L2Cache, "Token protocol")
       peek(requestNetwork_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
           if (in_msg.Requestor == machineID) {
-            trigger(Event:Own_GETX, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:Own_GETX, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           } else {
-            trigger(Event:Fwd_GETX, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:Fwd_GETX, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:Fwd_GETS, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Fwd_GETS, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if(in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:Fwd_DMA, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Fwd_DMA, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Inv, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
-          trigger(Event:Writeback_Ack, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Writeback_Ack, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
-          trigger(Event:Writeback_Nack, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Writeback_Nack, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -589,26 +589,26 @@ machine(L2Cache, "Token protocol")
       peek(L1requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:L1_GETX, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:L1_GETX, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
-            trigger(Event:L1_GETS, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:L1_GETS, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTO) {
-          trigger(Event:L1_PUTO, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:L1_PUTO, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
-          trigger(Event:L1_PUTX, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:L1_PUTX, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTS) {
-          Entry cache_entry := getCacheEntry(in_msg.Address);
-          if (isOnlySharer(cache_entry, in_msg.Address, in_msg.Requestor)) {
-            trigger(Event:L1_PUTS_only, in_msg.Address,
-                    cache_entry, TBEs[in_msg.Address]);
+          Entry cache_entry := getCacheEntry(in_msg.Addr);
+          if (isOnlySharer(cache_entry, in_msg.Addr, in_msg.Requestor)) {
+            trigger(Event:L1_PUTS_only, in_msg.Addr,
+                    cache_entry, TBEs[in_msg.Addr]);
           }
           else {
-            trigger(Event:L1_PUTS, in_msg.Address,
-                    cache_entry, TBEs[in_msg.Address]);
+            trigger(Event:L1_PUTS, in_msg.Addr,
+                    cache_entry, TBEs[in_msg.Addr]);
           }
         } else {
           error("Unexpected message");
@@ -625,52 +625,52 @@ machine(L2Cache, "Token protocol")
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceResponseType:ACK) {
           if (in_msg.SenderMachine == MachineType:L2Cache) {
-            trigger(Event:ExtAck, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:ExtAck, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           }
           else {
-            trigger(Event:IntAck, in_msg.Address,
-                    getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+            trigger(Event:IntAck, in_msg.Addr,
+                    getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Data, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Data_Exclusive, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Data_Exclusive, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-          trigger(Event:Unblock, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Unblock, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE) {
-          trigger(Event:Exclusive_Unblock, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:Exclusive_Unblock, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
-          Entry cache_entry := getCacheEntry(in_msg.Address);
+          Entry cache_entry := getCacheEntry(in_msg.Addr);
           if (is_invalid(cache_entry) &&
-                   L2cache.cacheAvail(in_msg.Address) == false) {
-            trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Address),
-                    getCacheEntry(L2cache.cacheProbe(in_msg.Address)),
-                    TBEs[L2cache.cacheProbe(in_msg.Address)]);
+                   L2cache.cacheAvail(in_msg.Addr) == false) {
+            trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
+                    getCacheEntry(L2cache.cacheProbe(in_msg.Addr)),
+                    TBEs[L2cache.cacheProbe(in_msg.Addr)]);
           }
           else {
-            trigger(Event:L1_WBDIRTYDATA, in_msg.Address,
-                    cache_entry, TBEs[in_msg.Address]);
+            trigger(Event:L1_WBDIRTYDATA, in_msg.Addr,
+                    cache_entry, TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA) {
-          Entry cache_entry := getCacheEntry(in_msg.Address);
+          Entry cache_entry := getCacheEntry(in_msg.Addr);
           if (is_invalid(cache_entry) &&
-                   L2cache.cacheAvail(in_msg.Address) == false) {
-            trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Address),
-                    getCacheEntry(L2cache.cacheProbe(in_msg.Address)),
-                    TBEs[L2cache.cacheProbe(in_msg.Address)]);
+                   L2cache.cacheAvail(in_msg.Addr) == false) {
+            trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
+                    getCacheEntry(L2cache.cacheProbe(in_msg.Addr)),
+                    TBEs[L2cache.cacheProbe(in_msg.Addr)]);
           }
           else {
-            trigger(Event:L1_WBCLEANDATA, in_msg.Address,
-                    cache_entry, TBEs[in_msg.Address]);
+            trigger(Event:L1_WBCLEANDATA, in_msg.Addr,
+                    cache_entry, TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
-          trigger(Event:DmaAck, in_msg.Address,
-                  getCacheEntry(in_msg.Address), TBEs[in_msg.Address]);
+          trigger(Event:DmaAck, in_msg.Addr,
+                  getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -684,7 +684,7 @@ machine(L2Cache, "Token protocol")
   action(a_issueGETS, "a", desc="issue local request globally") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.RequestorMachine := MachineType:L2Cache;
         out_msg.Requestor := machineID;
@@ -697,7 +697,7 @@ machine(L2Cache, "Token protocol")
   action(a_issueGETX, "\a", desc="issue local request globally") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.RequestorMachine := MachineType:L2Cache;
         out_msg.Requestor := machineID;
@@ -709,7 +709,7 @@ machine(L2Cache, "Token protocol")
 
   action(b_issuePUTX, "b", desc="Issue PUTX") {
     enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.RequestorMachine := MachineType:L2Cache;
       out_msg.Requestor := machineID;
@@ -720,7 +720,7 @@ machine(L2Cache, "Token protocol")
 
   action(b_issuePUTO, "\b", desc="Issue PUTO") {
     enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTO;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L2Cache;
@@ -732,7 +732,7 @@ machine(L2Cache, "Token protocol")
   /* PUTO, but local sharers exist */
   action(b_issuePUTO_ls, "\bb", desc="Issue PUTO") {
     enqueue(globalRequestNetwork_out, RequestMsg, latency=request_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTO_SHARERS;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L2Cache;
@@ -744,7 +744,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendDataFromTBEToL1GETS, "c", desc="Send data from TBE to L1 requestors in TBE") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.addNetDest(tbe.L1_GetS_IDs);
@@ -761,7 +761,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendDataFromTBEToL1GETX, "\c", desc="Send data from TBE to L1 requestors in TBE") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -778,7 +778,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendExclusiveDataFromTBEToL1GETS, "\cc", desc="Send data from TBE to L1 requestors in TBE") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -792,7 +792,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendDataFromTBEToFwdGETX, "cc", desc="Send data from TBE to external GETX") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -808,7 +808,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(tbe));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -827,7 +827,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendDataFromTBEToFwdGETS, "ccc", desc="Send data from TBE to external GETX") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA;
       out_msg.Sender := machineID;
       out_msg.Destination.addNetDest(tbe.Fwd_GetS_IDs);
@@ -845,7 +845,7 @@ machine(L2Cache, "Token protocol")
   action(c_sendExclusiveDataFromTBEToFwdGETS, "\ccc", desc="Send data from TBE to external GETX") {
     assert(is_valid(tbe));
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -863,7 +863,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -883,7 +883,7 @@ machine(L2Cache, "Token protocol")
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:L2Cache;
@@ -902,7 +902,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:L2Cache;
@@ -922,7 +922,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -941,7 +941,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -955,7 +955,7 @@ machine(L2Cache, "Token protocol")
   action(e_sendAck, "e", desc="Send ack with the tokens we've collected thus far.") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:ACK;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -969,7 +969,7 @@ machine(L2Cache, "Token protocol")
   action(e_sendAckToL1Requestor, "\e", desc="Send ack with the tokens we've collected thus far.") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:L2Cache;
@@ -983,7 +983,7 @@ machine(L2Cache, "Token protocol")
   action(e_sendAckToL1RequestorFromTBE, "eee", desc="Send ack with the tokens we've collected thus far.") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:ACK;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
@@ -1005,7 +1005,7 @@ machine(L2Cache, "Token protocol")
     }
 
     enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:INV;
       out_msg.Requestor := machineID;
       out_msg.RequestorMachine := MachineType:L2Cache;
@@ -1026,7 +1026,7 @@ machine(L2Cache, "Token protocol")
 
     if (countLocalSharers(cache_entry, address) > 0) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := MachineType:L2Cache;
@@ -1058,7 +1058,7 @@ machine(L2Cache, "Token protocol")
           }
 
           enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := CoherenceRequestType:INV;
             out_msg.Requestor := in_msg.Requestor;
             out_msg.RequestorMachine := MachineType:L1Cache;
@@ -1084,7 +1084,7 @@ machine(L2Cache, "Token protocol")
       }
     }
     enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := tbe.L1_GetX_ID;
         out_msg.RequestorMachine := MachineType:L1Cache;
@@ -1097,7 +1097,7 @@ machine(L2Cache, "Token protocol")
 
   action(f_sendUnblock, "f", desc="Send unblock to global directory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Sender := machineID;
@@ -1109,7 +1109,7 @@ machine(L2Cache, "Token protocol")
 
   action(f_sendExclusiveUnblock, "\f", desc="Send unblock to global directory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Sender := machineID;
@@ -1121,7 +1121,7 @@ machine(L2Cache, "Token protocol")
 
   action(g_recordLocalSharer, "g", desc="Record new local sharer from unblock message") {
     peek(responseNetwork_in, ResponseMsg) {
-      recordLocalSharerInDir(cache_entry, in_msg.Address, in_msg.Sender);
+      recordLocalSharerInDir(cache_entry, in_msg.Addr, in_msg.Sender);
     }
   }
 
@@ -1137,13 +1137,13 @@ machine(L2Cache, "Token protocol")
 
   action(gg_clearSharerFromL1Response, "\gg", desc="Clear sharer from L1 response queue") {
     peek(responseNetwork_in, ResponseMsg) {
-      removeSharerFromDir(cache_entry, in_msg.Address, in_msg.Sender);
+      removeSharerFromDir(cache_entry, in_msg.Addr, in_msg.Sender);
     }
   }
 
   action(gg_clearOwnerFromL1Response, "g\g", desc="Clear sharer from L1 response queue") {
     peek(responseNetwork_in, ResponseMsg) {
-      removeOwnerFromDir(cache_entry, in_msg.Address, in_msg.Sender);
+      removeOwnerFromDir(cache_entry, in_msg.Addr, in_msg.Sender);
     }
   }
 
@@ -1192,11 +1192,11 @@ machine(L2Cache, "Token protocol")
   action(j_forwardGlobalRequestToLocalOwner, "j", desc="Forward external request to local owner") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := MachineType:L2Cache;
-        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
+        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Addr));
         out_msg.Type := in_msg.Type;
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 0 - 1;
@@ -1207,11 +1207,11 @@ machine(L2Cache, "Token protocol")
   action(jd_forwardDmaRequestToLocalOwner, "jd", desc="Forward dma request to local owner") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := in_msg.RequestorMachine;
-        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
+        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Addr));
         out_msg.Type := in_msg.Type;
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 0 - 1;
@@ -1223,12 +1223,12 @@ machine(L2Cache, "Token protocol")
   action(k_forwardLocalGETSToLocalSharer, "k", desc="Forward local request to local sharer/owner") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := MachineType:L1Cache;
         // should randomize this so one node doesn't get abused more than others
-        out_msg.Destination.add(localDirectory[in_msg.Address].Sharers.smallestElement(MachineType:L1Cache));
+        out_msg.Destination.add(localDirectory[in_msg.Addr].Sharers.smallestElement(MachineType:L1Cache));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
       }
     }
@@ -1237,7 +1237,7 @@ machine(L2Cache, "Token protocol")
   action(k_forwardLocalGETXToLocalOwner, "\k", desc="Forward local request to local owner") {
     enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:GETX;
       out_msg.Requestor := tbe.L1_GetX_ID;
       out_msg.RequestorMachine := MachineType:L1Cache;
@@ -1251,11 +1251,11 @@ machine(L2Cache, "Token protocol")
   action(kk_forwardLocalGETXToLocalExclusive, "kk", desc="Forward local request to local owner") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := MachineType:L1Cache;
-        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
+        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Addr));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
         out_msg.Acks := 1;
       }
@@ -1265,11 +1265,11 @@ machine(L2Cache, "Token protocol")
   action(kk_forwardLocalGETSToLocalOwner, "\kk", desc="Forward local request to local owner") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := MachineType:L1Cache;
-        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Address));
+        out_msg.Destination.add(getLocalOwner(cache_entry, in_msg.Addr));
         out_msg.MessageSize := MessageSizeType:Forwarded_Control;
       }
     }
@@ -1279,7 +1279,7 @@ machine(L2Cache, "Token protocol")
   action(l_writebackAckNeedData, "l", desc="Send writeback ack to L1 requesting data") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         // out_msg.Type := CoherenceResponseType:WRITEBACK_SEND_DATA;
         out_msg.Type := CoherenceRequestType:WB_ACK_DATA;
         out_msg.Requestor := machineID;
@@ -1293,7 +1293,7 @@ machine(L2Cache, "Token protocol")
   action(l_writebackAckDropData, "\l", desc="Send writeback ack to L1 indicating to drop data") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         // out_msg.Type := CoherenceResponseType:WRITEBACK_ACK;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := machineID;
@@ -1307,7 +1307,7 @@ machine(L2Cache, "Token protocol")
   action(ll_writebackNack, "\ll", desc="Send writeback nack to L1") {
     peek(L1requestNetwork_in, RequestMsg) {
       enqueue( localRequestNetwork_out, RequestMsg, latency=response_latency ) {
-        out_msg.Address := in_msg.Address;
+        out_msg.Addr := in_msg.Addr;
         out_msg.Type := CoherenceRequestType:WB_NACK;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := MachineType:L2Cache;
@@ -1359,7 +1359,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(tbe));
     if (tbe.NumIntPendingAcks == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS;
       }
     }
@@ -1369,7 +1369,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(tbe));
     if (tbe.NumExtPendingAcks == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS;
       }
     }
@@ -1379,7 +1379,7 @@ machine(L2Cache, "Token protocol")
   action( qq_sendDataFromTBEToMemory, "qq", desc="Send data from TBE to directory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:L2Cache;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -1512,7 +1512,7 @@ machine(L2Cache, "Token protocol")
 
   action(da_sendDmaAckUnblock, "da", desc="Send dma ack to global directory") {
     enqueue(responseNetwork_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DMA_ACK;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Sender := machineID;
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 219cb51b7..753acc58d 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -224,28 +224,28 @@ machine(Directory, "Directory protocol")
     if (unblockNetwork_in.isReady()) {
       peek(unblockNetwork_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-          if (getDirectoryEntry(in_msg.Address).WaitingUnblocks == 1) {
-            trigger(Event:Last_Unblock, in_msg.Address,
-                    TBEs[in_msg.Address]);
+          if (getDirectoryEntry(in_msg.Addr).WaitingUnblocks == 1) {
+            trigger(Event:Last_Unblock, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else {
-            trigger(Event:Unblock, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Unblock, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           }
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE) {
-          trigger(Event:Exclusive_Unblock, in_msg.Address,
-                  TBEs[in_msg.Address]);
+          trigger(Event:Exclusive_Unblock, in_msg.Addr,
+                  TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
-          trigger(Event:Dirty_Writeback, in_msg.Address,
-                  TBEs[in_msg.Address]);
+          trigger(Event:Dirty_Writeback, in_msg.Addr,
+                  TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:WRITEBACK_CLEAN_ACK) {
-          trigger(Event:Clean_Writeback, in_msg.Address,
-                  TBEs[in_msg.Address]);
+          trigger(Event:Clean_Writeback, in_msg.Addr,
+                  TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Data, in_msg.Address,
-                  TBEs[in_msg.Address]);
+          trigger(Event:Data, in_msg.Addr,
+                  TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
-          trigger(Event:DMA_ACK, in_msg.Address,
-                  TBEs[in_msg.Address]);
+          trigger(Event:DMA_ACK, in_msg.Addr,
+                  TBEs[in_msg.Addr]);
         } else {
           error("Invalid message");
         }
@@ -257,21 +257,21 @@ machine(Directory, "Directory protocol")
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:GETS, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:GETS, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:GETX, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:GETX, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTX) {
-          trigger(Event:PUTX, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:PUTX, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTO) {
-          trigger(Event:PUTO, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:PUTO, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) {
-          trigger(Event:PUTO_SHARERS, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:PUTO_SHARERS, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:DMA_READ, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
-          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else {
           error("Invalid message");
         }
@@ -284,9 +284,9 @@ machine(Directory, "Directory protocol")
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -300,7 +300,7 @@ machine(Directory, "Directory protocol")
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := MachineType:Directory;
@@ -313,7 +313,7 @@ machine(Directory, "Directory protocol")
   action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_NACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := MachineType:Directory;
@@ -339,11 +339,11 @@ machine(Directory, "Directory protocol")
   action(d_sendDataMsg, "d", desc="Send data to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:Directory;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
-        //out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        //out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         out_msg.DataBlk := in_msg.DataBlk;
         out_msg.Dirty := false; // By definition, the block is now clean
         out_msg.Acks := in_msg.Acks;
@@ -360,11 +360,11 @@ machine(Directory, "Directory protocol")
   action(p_fwdDataToDMA, "\d", desc="Send data to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Sender := machineID;
         out_msg.SenderMachine := MachineType:Directory;
         out_msg.Destination.add(in_msg.Requestor);
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         out_msg.Dirty := false; // By definition, the block is now clean
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -384,11 +384,11 @@ machine(Directory, "Directory protocol")
   action(f_forwardRequest, "f", desc="Forward request to owner") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.RequestorMachine := machineIDToMachineType(in_msg.Requestor);
-        out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
+        out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Addr).Owner);
         out_msg.Acks := getDirectoryEntry(address).Sharers.count();
         if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
           out_msg.Acks := out_msg.Acks - 1;
@@ -401,11 +401,11 @@ machine(Directory, "Directory protocol")
   action(f_forwardRequestDirIsRequestor, "\f", desc="Forward request to owner") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Requestor := machineID;
         out_msg.RequestorMachine := machineIDToMachineType(in_msg.Requestor);
-        out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
+        out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Addr).Owner);
         out_msg.Acks := getDirectoryEntry(address).Sharers.count();
         if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
           out_msg.Acks := out_msg.Acks - 1;
@@ -417,16 +417,16 @@ machine(Directory, "Directory protocol")
 
   action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") {
     peek(requestQueue_in, RequestMsg) {
-      if ((getDirectoryEntry(in_msg.Address).Sharers.count() > 1) ||
-          ((getDirectoryEntry(in_msg.Address).Sharers.count() > 0) &&
-           (getDirectoryEntry(in_msg.Address).Sharers.isElement(in_msg.Requestor) == false))) {
+      if ((getDirectoryEntry(in_msg.Addr).Sharers.count() > 1) ||
+          ((getDirectoryEntry(in_msg.Addr).Sharers.count() > 0) &&
+           (getDirectoryEntry(in_msg.Addr).Sharers.isElement(in_msg.Requestor) == false))) {
         enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:INV;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.RequestorMachine := machineIDToMachineType(in_msg.Requestor);
-          // out_msg.Destination := getDirectoryEntry(in_msg.Address).Sharers;
-          out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Sharers);
+          // out_msg.Destination := getDirectoryEntry(in_msg.Addr).Sharers;
+          out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Addr).Sharers);
           out_msg.Destination.remove(in_msg.Requestor);
           out_msg.MessageSize := MessageSizeType:Invalidate_Control;
         }
@@ -446,17 +446,17 @@ machine(Directory, "Directory protocol")
     peek(unblockNetwork_in, ResponseMsg) {
       assert(in_msg.Dirty);
       assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
-      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
+      getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
   action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") {
      peek(unblockNetwork_in, ResponseMsg) {
-      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
+      getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
  }
 
@@ -470,9 +470,9 @@ machine(Directory, "Directory protocol")
       // message so we can assert the clean data matches the datablock
       // in memory
       DPRINTF(RubySlicc, "Address: %s, MsgDataBlock: %s MemoryDataBlock: %s\n",
-              in_msg.Address, in_msg.DataBlk,
-              getDirectoryEntry(in_msg.Address).DataBlk);
-      assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk,
+              getDirectoryEntry(in_msg.Addr).DataBlk);
+      assert(getDirectoryEntry(in_msg.Addr).DataBlk == in_msg.DataBlk);
     }
   }
 
@@ -498,11 +498,11 @@ machine(Directory, "Directory protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         out_msg.MessageSize := in_msg.MessageSize;
         //out_msg.Prefetch := false;
         // These are not used by memory but are passed back here with the read data:
@@ -520,7 +520,7 @@ machine(Directory, "Directory protocol")
   action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
     peek(unblockNetwork_in, ResponseMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.Sender := machineID;
         if (is_valid(tbe)) {
@@ -540,7 +540,7 @@ machine(Directory, "Directory protocol")
   action(qw_queueMemoryWBRequest2, "/qw", desc="Queue off-chip writeback request") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -567,7 +567,7 @@ machine(Directory, "Directory protocol")
   action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along with Inv Ack count") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:Directory;
       out_msg.Destination.add(in_msg.Requestor);
@@ -582,7 +582,7 @@ machine(Directory, "Directory protocol")
   action(a_sendDMAAck2, "\aa", desc="Send DMA Ack that write completed, along with Inv Ack count") {
     peek(unblockNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.SenderMachine := MachineType:Directory;
       if (is_valid(tbe)) {
@@ -598,7 +598,7 @@ machine(Directory, "Directory protocol")
 
   action(l_writeDMADataToMemory, "\l", desc="Write data from a DMA_WRITE to memory") {
     peek(requestQueue_in, RequestMsg) {
-      getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
+      getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
     }
   }
 
@@ -612,7 +612,7 @@ machine(Directory, "Directory protocol")
     peek (requestQueue_in, RequestMsg) {
       TBEs.allocate(address);
       set_tbe(TBEs[address]);
-      tbe.PhysicalAddress := in_msg.Address;
+      tbe.PhysicalAddress := in_msg.Addr;
       tbe.Len := in_msg.Len;
       tbe.DataBlk := in_msg.DataBlk;
       tbe.Requestor := in_msg.Requestor;
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index d96276245..f79f0a535 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -120,15 +120,15 @@ machine(DMA, "DMA Controller")
     if (dmaResponseQueue_in.isReady()) {
       peek( dmaResponseQueue_in, ResponseMsg) {
         if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
-          trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:DMA_Ack, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
        in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:Data, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address),
-                  TBEs[makeLineAddress(in_msg.Address)]);
+          trigger(Event:Inv_Ack, makeLineAddress(in_msg.Addr),
+                  TBEs[makeLineAddress(in_msg.Addr)]);
         } else {
           error("Invalid response type");
         }
@@ -141,7 +141,7 @@ machine(DMA, "DMA Controller")
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
         if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:All_Acks, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           error("Unexpected message");
         }
@@ -152,7 +152,7 @@ machine(DMA, "DMA Controller")
   action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-        out_msg.Address := in_msg.PhysicalAddress;
+        out_msg.Addr := in_msg.PhysicalAddress;
         out_msg.Type := CoherenceRequestType:DMA_READ;
         out_msg.DataBlk := in_msg.DataBlk;
         out_msg.Len := in_msg.Len;
@@ -167,7 +167,7 @@ machine(DMA, "DMA Controller")
   action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
-          out_msg.Address := in_msg.PhysicalAddress;
+          out_msg.Addr := in_msg.PhysicalAddress;
           out_msg.Type := CoherenceRequestType:DMA_WRITE;
           out_msg.DataBlk := in_msg.DataBlk;
           out_msg.Len := in_msg.Len;
@@ -187,7 +187,7 @@ machine(DMA, "DMA Controller")
     assert(is_valid(tbe));
     if (tbe.NumAcks == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS;
       }
     }
@@ -202,7 +202,7 @@ machine(DMA, "DMA Controller")
 
   action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
     enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Sender := machineID;
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm
index e428be7f7..6452aa9f9 100644
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -69,7 +69,7 @@ enumeration(TriggerType, desc="...") {
 
 // TriggerMsg
 structure(TriggerMsg, desc="...", interface="Message") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   TriggerType Type,            desc="Type of trigger";
 
   bool functionalRead(Packet *pkt) {
@@ -85,7 +85,7 @@ structure(TriggerMsg, desc="...", interface="Message") {
 
 // RequestMsg (and also forwarded requests)
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   int Len,                     desc="Length of Request";
   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
   MachineID Requestor,            desc="Node who initiated the request";
@@ -101,20 +101,20 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
     // Read only those messages that contain the data
     if (Type == CoherenceRequestType:DMA_READ ||
         Type == CoherenceRequestType:DMA_WRITE) {
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
     return false;
   }
 
   bool functionalWrite(Packet *pkt) {
     // No check required since all messages are written
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
 // ResponseMsg (and also unblock requests)
 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceResponseType Type,  desc="Type of response (Ack, Data, etc)";
   MachineID Sender,               desc="Node who sent the data";
   MachineType SenderMachine,   desc="type of component sending msg";
@@ -130,13 +130,13 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA ||
         Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
     return false;
   }
 
   bool functionalWrite(Packet *pkt) {
     // No check required since all messages are written
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 89b21e2f6..935fe03c7 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -142,7 +142,7 @@ machine(L1Cache, "Token protocol")
 
   // TBE fields
   structure(TBE, desc="...") {
-    Address address,                      desc="Physical address for this TBE";
+    Address Addr,                      desc="Physical address for this TBE";
     State TBEState,                       desc="Transient state";
     int IssueCount,      default="0",     desc="The number of times we've issued a request for this line.";
     Address PC,                           desc="Program counter of request";
@@ -151,7 +151,7 @@ machine(L1Cache, "Token protocol")
     bool ExternalResponse, default="false", desc="Response came from an external controller";
     bool IsAtomic, default="false",       desc="Request was an atomic request";
 
-    AccessType AccessType,                desc="Type of request (used for profiling)";
+    AccessType TypeOfAccess,                desc="Type of request (used for profiling)";
     Cycles IssueTime,                       desc="Time the request was issued";
     RubyAccessMode AccessMode,    desc="user/supervisor access type";
     PrefetchBit Prefetch,         desc="Is this a prefetch request";
@@ -485,47 +485,47 @@ machine(L1Cache, "Token protocol")
   // Persistent Network
   in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
     if (persistentNetwork_in.isReady()) {
-      peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
+      peek(persistentNetwork_in, PersistentMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
 
         // Apply the lockdown or unlockdown message to the table
         if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
-          persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
+          persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Write);
         } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
-          persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
+          persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Read);
         } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
-          persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
+          persistentTable.persistentRequestUnlock(in_msg.Addr, in_msg.Requestor);
         } else {
           error("Unexpected message");
         }
 
         // React to the message based on the current state of the table
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L1_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L1_TBEs[in_msg.Addr];
 
-        if (persistentTable.isLocked(in_msg.Address)) {
-          if (persistentTable.findSmallest(in_msg.Address) == machineID) {
+        if (persistentTable.isLocked(in_msg.Addr)) {
+          if (persistentTable.findSmallest(in_msg.Addr) == machineID) {
             // Our Own Lock - this processor is highest priority
-            trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
+            trigger(Event:Own_Lock_or_Unlock, in_msg.Addr,
                     cache_entry, tbe);
           } else {
-            if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
+            if (persistentTable.typeOfSmallest(in_msg.Addr) == AccessType:Read) {
               if (getTokens(cache_entry) == 1 ||
                   getTokens(cache_entry) == (max_tokens() / 2) + 1) {
-                trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
+                trigger(Event:Persistent_GETS_Last_Token, in_msg.Addr,
                         cache_entry, tbe);
               } else {
-                trigger(Event:Persistent_GETS, in_msg.Address,
+                trigger(Event:Persistent_GETS, in_msg.Addr,
                         cache_entry, tbe);
               }
             } else {
-              trigger(Event:Persistent_GETX, in_msg.Address,
+              trigger(Event:Persistent_GETX, in_msg.Addr,
                       cache_entry, tbe);
             }
           }
         } else {
           // Unlock case - no entries in the table
-          trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
+          trigger(Event:Own_Lock_or_Unlock, in_msg.Addr,
                   cache_entry, tbe);
         }
       }
@@ -535,43 +535,43 @@ machine(L1Cache, "Token protocol")
   // Response Network
   in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
     if (responseNetwork_in.isReady()) {
-      peek(responseNetwork_in, ResponseMsg, block_on="Address") {
+      peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L1_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L1_TBEs[in_msg.Addr];
 
         // Mark TBE flag if response received off-chip.  Use this to update average latency estimate
         if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
 
-          if (in_msg.Sender == mapAddressToRange(in_msg.Address,
+          if (in_msg.Sender == mapAddressToRange(in_msg.Addr,
                                                  MachineType:L2Cache,
                                                  l2_select_low_bit,
                                                  l2_select_num_bits)) {
 
             // came from an off-chip L2 cache
             if (is_valid(tbe)) {
-               // L1_TBEs[in_msg.Address].ExternalResponse := true;
-               // profile_offchipL2_response(in_msg.Address);
+               // L1_TBEs[in_msg.Addr].ExternalResponse := true;
+               // profile_offchipL2_response(in_msg.Addr);
             }
           }
           else {
-               // profile_onchipL2_response(in_msg.Address );
+               // profile_onchipL2_response(in_msg.Addr );
           }
         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:Directory ) {
           if (is_valid(tbe)) {
             setExternalResponse(tbe);
-            // profile_memory_response( in_msg.Address);
+            // profile_memory_response( in_msg.Addr);
           }
         } else if ( machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
           //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
             //if (is_valid(tbe)) {
                // tbe.ExternalResponse := true;
-               // profile_offchipL1_response(in_msg.Address );
+               // profile_offchipL1_response(in_msg.Addr );
             //}
           //}
           //else {
-               // profile_onchipL1_response(in_msg.Address );
+               // profile_onchipL1_response(in_msg.Addr );
           //}
         } else {
           error("unexpected SenderMachine");
@@ -581,21 +581,21 @@ machine(L1Cache, "Token protocol")
         if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
           if (in_msg.Type == CoherenceResponseType:ACK) {
             assert(in_msg.Tokens < (max_tokens() / 2));
-            trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
-            trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Data_Owner, in_msg.Addr, cache_entry, tbe);
           } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
             assert(in_msg.Tokens < (max_tokens() / 2));
-            trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Data_Shared, in_msg.Addr, cache_entry, tbe);
           } else {
             error("Unexpected message");
           }
         } else {
           if (in_msg.Type == CoherenceResponseType:ACK) {
             assert(in_msg.Tokens < (max_tokens() / 2));
-            trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Ack_All_Tokens, in_msg.Addr, cache_entry, tbe);
           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER || in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-            trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
+            trigger(Event:Data_All_Tokens, in_msg.Addr, cache_entry, tbe);
           } else {
             error("Unexpected message");
           }
@@ -607,40 +607,40 @@ machine(L1Cache, "Token protocol")
   // Request Network
   in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
     if (requestNetwork_in.isReady()) {
-      peek(requestNetwork_in, RequestMsg, block_on="Address") {
+      peek(requestNetwork_in, RequestMsg, block_on="Addr") {
         assert(in_msg.Destination.isElement(machineID));
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := L1_TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := L1_TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceRequestType:GETX) {
           if (in_msg.isLocal) {
-            trigger(Event:Transient_Local_GETX, in_msg.Address,
+            trigger(Event:Transient_Local_GETX, in_msg.Addr,
                     cache_entry, tbe);
           }
           else {
-            trigger(Event:Transient_GETX, in_msg.Address,
+            trigger(Event:Transient_GETX, in_msg.Addr,
                     cache_entry, tbe);
           }
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
           if (getTokens(cache_entry) == 1 ||
               getTokens(cache_entry) == (max_tokens() / 2) + 1) {
             if (in_msg.isLocal) {
-              trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
+              trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Addr,
                       cache_entry, tbe);
             }
             else {
-              trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
+              trigger(Event:Transient_GETS_Last_Token, in_msg.Addr,
                       cache_entry, tbe);
             }
           }
           else {
             if (in_msg.isLocal) {
-              trigger(Event:Transient_Local_GETS, in_msg.Address,
+              trigger(Event:Transient_Local_GETS, in_msg.Addr,
                       cache_entry, tbe);
             }
             else {
-              trigger(Event:Transient_GETS, in_msg.Address,
+              trigger(Event:Transient_GETS, in_msg.Addr,
                       cache_entry, tbe);
             }
           }
@@ -740,7 +740,7 @@ machine(L1Cache, "Token protocol")
         // Issue a persistent request if possible
         if (okToIssueStarving(address, machineID) && (starving == false)) {
           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
             out_msg.Requestor := machineID;
             out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -766,7 +766,7 @@ machine(L1Cache, "Token protocol")
           starving := true;
 
           if (tbe.IssueCount == 0) {
-            //profile_persistent_prediction(address, tbe.AccessType);
+            //profile_persistent_prediction(address, tbe.TypeOfAccess);
           }
 
           // Update outstanding requests
@@ -793,7 +793,7 @@ machine(L1Cache, "Token protocol")
       } else {
         // Make a normal request
         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETS;
           out_msg.Requestor := machineID;
           out_msg.Destination.add(mapAddressToRange(address,
@@ -813,7 +813,7 @@ machine(L1Cache, "Token protocol")
 
         // send to other local L1s, with local bit set
         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETS;
           out_msg.Requestor := machineID;
           //
@@ -861,7 +861,7 @@ machine(L1Cache, "Token protocol")
         // Issue a persistent request if possible
         if ( okToIssueStarving(address, machineID) && (starving == false)) {
           enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
             out_msg.Requestor := machineID;
             out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -891,7 +891,7 @@ machine(L1Cache, "Token protocol")
           outstandingPersistentRequests := outstandingPersistentRequests + 1;
 
           if (tbe.IssueCount == 0) {
-            //profile_persistent_prediction(address, tbe.AccessType);
+            //profile_persistent_prediction(address, tbe.TypeOfAccess);
           }
 
           // Increment IssueCount
@@ -914,7 +914,7 @@ machine(L1Cache, "Token protocol")
       } else  {
         // Make a normal request
         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETX;
           out_msg.Requestor := machineID;
 
@@ -936,7 +936,7 @@ machine(L1Cache, "Token protocol")
 
         // send to other local L1s too
         enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETX;
           out_msg.Requestor := machineID;
           out_msg.isLocal := true;
@@ -977,7 +977,7 @@ machine(L1Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       // FIXME, should use a 3rd vnet
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Sender := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
@@ -992,7 +992,7 @@ machine(L1Cache, "Token protocol")
   action(c_ownedReplacement, "c", desc="Issue writeback") {
     assert(is_valid(cache_entry));
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
 
       out_msg.Destination.add(mapAddressToRange(address,
@@ -1017,7 +1017,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert (cache_entry.Tokens > 0);
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Sender := machineID;
 
         out_msg.Destination.add(mapAddressToRange(address,
@@ -1040,7 +1040,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     if (cache_entry.Tokens > 0) {
       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Sender := machineID;
 
         out_msg.Destination.add(mapAddressToRange(address,
@@ -1066,7 +1066,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -1090,7 +1090,7 @@ machine(L1Cache, "Token protocol")
     peek(requestNetwork_in, RequestMsg) {
       if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_SHARED;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
@@ -1108,7 +1108,7 @@ machine(L1Cache, "Token protocol")
       }
       else if (cache_entry.Tokens > 1) {
         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_SHARED;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
@@ -1132,7 +1132,7 @@ machine(L1Cache, "Token protocol")
     peek(requestNetwork_in, RequestMsg) {
     assert(is_valid(cache_entry));
       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -1155,7 +1155,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     if (cache_entry.Tokens > 0) {
       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (cache_entry.Tokens > (max_tokens() / 2)) {
           out_msg.Type := CoherenceResponseType:DATA_OWNER;
         } else {
@@ -1177,7 +1177,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert(cache_entry.Tokens > 0);
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_OWNER;
       out_msg.Sender := machineID;
       out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -1196,7 +1196,7 @@ machine(L1Cache, "Token protocol")
     assert(cache_entry.Tokens > 0);
     if (cache_entry.Tokens > 1) {
       enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (cache_entry.Tokens > (max_tokens() / 2)) {
           out_msg.Type := CoherenceResponseType:DATA_OWNER;
         } else {
@@ -1226,7 +1226,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert(cache_entry.Tokens > ((max_tokens() / 2) + 1));
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -1251,7 +1251,7 @@ machine(L1Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert(cache_entry.Tokens == ((max_tokens() / 2) + 1));
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -1271,7 +1271,7 @@ machine(L1Cache, "Token protocol")
       // assert(persistentTable.findSmallest(address) != id); // Make sure we never bounce tokens to ourself
       // FIXME, should use a 3rd vnet in some cases
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -1343,7 +1343,7 @@ machine(L1Cache, "Token protocol")
     tbe.IssueCount := 0;
     peek(mandatoryQueue_in, RubyRequest) {
       tbe.PC := in_msg.ProgramCounter;
-      tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
+      tbe.TypeOfAccess := cache_request_type_to_access_type(in_msg.Type);
       if (in_msg.Type == RubyRequestType:ATOMIC) {
         tbe.IsAtomic := true;
       }
@@ -1391,7 +1391,7 @@ machine(L1Cache, "Token protocol")
 
   action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") {
     enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-       out_msg.Address := address;
+       out_msg.Addr := address;
        out_msg.Type := CoherenceResponseType:INV;
        out_msg.Tokens := 0;
        out_msg.Sender := machineID;
@@ -1410,7 +1410,7 @@ machine(L1Cache, "Token protocol")
       assert(is_valid(cache_entry));
       assert(in_msg.Tokens != 0);
       DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
-              in_msg.Address, in_msg.Tokens);
+              in_msg.Addr, in_msg.Tokens);
       cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
       DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
 
@@ -1427,7 +1427,7 @@ machine(L1Cache, "Token protocol")
       // assert(starving == true);
       outstandingRequests := outstandingRequests - 1;
       enqueue(persistentNetwork_out, PersistentMsg, latency = l1_request_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
         out_msg.Requestor := machineID;
         out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -1459,13 +1459,13 @@ machine(L1Cache, "Token protocol")
 
     // Profile
     //if (tbe.WentPersistent) {
-    //  profile_token_retry(address, tbe.AccessType, 2);
+    //  profile_token_retry(address, tbe.TypeOfAccess, 2);
     //}
     //else {
-    //  profile_token_retry(address, tbe.AccessType, 1);
+    //  profile_token_retry(address, tbe.TypeOfAccess, 1);
     //}
 
-    //profile_token_retry(address, tbe.AccessType, tbe.IssueCount);
+    //profile_token_retry(address, tbe.TypeOfAccess, tbe.IssueCount);
     L1_TBEs.deallocate(address);
     unset_tbe();
   }
@@ -1475,7 +1475,7 @@ machine(L1Cache, "Token protocol")
     if (cache_entry.Tokens > 0) {
       peek(requestNetwork_in, RequestMsg) {
         enqueue(responseNetwork_out, ResponseMsg, latency = l1_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           if (cache_entry.Tokens > (max_tokens() / 2)) {
             out_msg.Type := CoherenceResponseType:DATA_OWNER;
           } else {
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index 60a9f699b..c7b2a618d 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -306,33 +306,33 @@ machine(L2Cache, "Token protocol")
         assert(in_msg.Destination.isElement(machineID));
 
         if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
-          persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
+          persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Write);
         } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
-          persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
+          persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Read);
         } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
-          persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
+          persistentTable.persistentRequestUnlock(in_msg.Addr, in_msg.Requestor);
         } else {
           error("Unexpected message");
         }
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
         // React to the message based on the current state of the table
-        if (persistentTable.isLocked(in_msg.Address)) {
+        if (persistentTable.isLocked(in_msg.Addr)) {
 
-          if (persistentTable.typeOfSmallest(in_msg.Address) == AccessType:Read) {
+          if (persistentTable.typeOfSmallest(in_msg.Addr) == AccessType:Read) {
             if (getTokens(cache_entry) == 1 ||
                 getTokens(cache_entry) == (max_tokens() / 2) + 1) {
-              trigger(Event:Persistent_GETS_Last_Token, in_msg.Address,
+              trigger(Event:Persistent_GETS_Last_Token, in_msg.Addr,
                       cache_entry);
             } else {
-              trigger(Event:Persistent_GETS, in_msg.Address, cache_entry);
+              trigger(Event:Persistent_GETS, in_msg.Addr, cache_entry);
             }
           } else {
-            trigger(Event:Persistent_GETX, in_msg.Address, cache_entry);
+            trigger(Event:Persistent_GETX, in_msg.Addr, cache_entry);
           }
         }
         else {
-            trigger(Event:Own_Lock_or_Unlock, in_msg.Address, cache_entry);
+            trigger(Event:Own_Lock_or_Unlock, in_msg.Addr, cache_entry);
         }
       }
     }
@@ -345,16 +345,16 @@ machine(L2Cache, "Token protocol")
       peek(requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
         if (in_msg.Type == CoherenceRequestType:GETX) {
-            trigger(Event:Transient_GETX, in_msg.Address, cache_entry);
+            trigger(Event:Transient_GETX, in_msg.Addr, cache_entry);
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
           if (getTokens(cache_entry) == 1) {
-            trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
+            trigger(Event:Transient_GETS_Last_Token, in_msg.Addr,
                     cache_entry);
           }
           else {
-            trigger(Event:Transient_GETS, in_msg.Address, cache_entry);
+            trigger(Event:Transient_GETS, in_msg.Addr, cache_entry);
           }
         } else {
           error("Unexpected message");
@@ -367,16 +367,16 @@ machine(L2Cache, "Token protocol")
     if (L1requestNetwork_in.isReady()) {
       peek(L1requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
-        Entry cache_entry := getCacheEntry(in_msg.Address);
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
         if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:L1_GETX, in_msg.Address, cache_entry);
+          trigger(Event:L1_GETX, in_msg.Addr, cache_entry);
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
           if (getTokens(cache_entry) == 1 ||
               getTokens(cache_entry) == (max_tokens() / 2) + 1) {
-            trigger(Event:L1_GETS_Last_Token, in_msg.Address, cache_entry);
+            trigger(Event:L1_GETS_Last_Token, in_msg.Addr, cache_entry);
           }
           else {
-            trigger(Event:L1_GETS, in_msg.Address, cache_entry);
+            trigger(Event:L1_GETS, in_msg.Addr, cache_entry);
           }
         } else {
           error("Unexpected message");
@@ -391,80 +391,80 @@ machine(L2Cache, "Token protocol")
     if (responseNetwork_in.isReady()) {
       peek(responseNetwork_in, ResponseMsg) {
         assert(in_msg.Destination.isElement(machineID));
-        Entry cache_entry := getCacheEntry(in_msg.Address);
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
 
         if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
           if (in_msg.Type == CoherenceResponseType:ACK) {
             assert(in_msg.Tokens < (max_tokens() / 2));
-            trigger(Event:Ack, in_msg.Address, cache_entry);
+            trigger(Event:Ack, in_msg.Addr, cache_entry);
           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
-            trigger(Event:Data_Owner, in_msg.Address, cache_entry);
+            trigger(Event:Data_Owner, in_msg.Addr, cache_entry);
           } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-            trigger(Event:Data_Shared, in_msg.Address, cache_entry);
+            trigger(Event:Data_Shared, in_msg.Addr, cache_entry);
           } else if (in_msg.Type == CoherenceResponseType:WB_TOKENS ||
                      in_msg.Type == CoherenceResponseType:WB_OWNED ||
                      in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
 
-            if (L2cache.cacheAvail(in_msg.Address) || is_valid(cache_entry)) {
+            if (L2cache.cacheAvail(in_msg.Addr) || is_valid(cache_entry)) {
 
               // either room is available or the block is already present
 
               if (in_msg.Type == CoherenceResponseType:WB_TOKENS) {
                 assert(in_msg.Dirty == false);
-                trigger(Event:Writeback_Tokens, in_msg.Address, cache_entry);
+                trigger(Event:Writeback_Tokens, in_msg.Addr, cache_entry);
               } else if (in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
                 assert(in_msg.Dirty == false);
-                trigger(Event:Writeback_Shared_Data, in_msg.Address, cache_entry);
+                trigger(Event:Writeback_Shared_Data, in_msg.Addr, cache_entry);
               }
               else if (in_msg.Type == CoherenceResponseType:WB_OWNED) {
                 //assert(in_msg.Dirty == false);
-                trigger(Event:Writeback_Owned, in_msg.Address, cache_entry);
+                trigger(Event:Writeback_Owned, in_msg.Addr, cache_entry);
               }
             }
             else {
                 trigger(Event:L2_Replacement,
-                        L2cache.cacheProbe(in_msg.Address),
-                        getCacheEntry(L2cache.cacheProbe(in_msg.Address)));
+                        L2cache.cacheProbe(in_msg.Addr),
+                        getCacheEntry(L2cache.cacheProbe(in_msg.Addr)));
             }
           } else if (in_msg.Type == CoherenceResponseType:INV) {
-            trigger(Event:L1_INV, in_msg.Address, cache_entry);
+            trigger(Event:L1_INV, in_msg.Addr, cache_entry);
           } else {
             error("Unexpected message");
           }
         } else {
           if (in_msg.Type == CoherenceResponseType:ACK) {
             assert(in_msg.Tokens < (max_tokens() / 2));
-            trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry);
+            trigger(Event:Ack_All_Tokens, in_msg.Addr, cache_entry);
           } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER ||
                      in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-            trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry);
+            trigger(Event:Data_All_Tokens, in_msg.Addr, cache_entry);
           } else if (in_msg.Type == CoherenceResponseType:WB_TOKENS ||
                      in_msg.Type == CoherenceResponseType:WB_OWNED ||
                      in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
-            if (L2cache.cacheAvail(in_msg.Address) || is_valid(cache_entry)) {
+            if (L2cache.cacheAvail(in_msg.Addr) || is_valid(cache_entry)) {
 
               // either room is available or the block is already present
 
               if (in_msg.Type == CoherenceResponseType:WB_TOKENS) {
                 assert(in_msg.Dirty == false);
-                assert(  (getState(cache_entry, in_msg.Address) != State:NP)
-                      && (getState(cache_entry, in_msg.Address) != State:I) );
-                trigger(Event:Writeback_All_Tokens, in_msg.Address, cache_entry);
+                assert(  (getState(cache_entry, in_msg.Addr) != State:NP)
+                      && (getState(cache_entry, in_msg.Addr) != State:I) );
+                trigger(Event:Writeback_All_Tokens, in_msg.Addr, cache_entry);
               } else if (in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
                 assert(in_msg.Dirty == false);
-                trigger(Event:Writeback_All_Tokens, in_msg.Address, cache_entry);
+                trigger(Event:Writeback_All_Tokens, in_msg.Addr, cache_entry);
               }
               else if (in_msg.Type == CoherenceResponseType:WB_OWNED) {
-                trigger(Event:Writeback_All_Tokens, in_msg.Address, cache_entry);
+                trigger(Event:Writeback_All_Tokens, in_msg.Addr, cache_entry);
               }
             }
             else {
                 trigger(Event:L2_Replacement,
-                        L2cache.cacheProbe(in_msg.Address),
-                        getCacheEntry(L2cache.cacheProbe(in_msg.Address)));
+                        L2cache.cacheProbe(in_msg.Addr),
+                        getCacheEntry(L2cache.cacheProbe(in_msg.Addr)));
             }
           } else if (in_msg.Type == CoherenceResponseType:INV) {
-            trigger(Event:L1_INV, in_msg.Address, cache_entry);
+            trigger(Event:L1_INV, in_msg.Addr, cache_entry);
           } else {
             DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Unexpected message");
@@ -483,9 +483,9 @@ machine(L2Cache, "Token protocol")
 
      // if this is a retry or no local sharers, broadcast normally
 
-     // if (in_msg.RetryNum > 0 || (in_msg.Type == CoherenceRequestType:GETX && exclusiveExists(in_msg.Address) == false) || (in_msg.Type == CoherenceRequestType:GETS && sharersExist(in_msg.Address) == false)) {
+     // if (in_msg.RetryNum > 0 || (in_msg.Type == CoherenceRequestType:GETX && exclusiveExists(in_msg.Addr) == false) || (in_msg.Type == CoherenceRequestType:GETS && sharersExist(in_msg.Addr) == false)) {
         enqueue(globalRequestNetwork_out, RequestMsg, latency=l2_request_latency) {
-           out_msg.Address := in_msg.Address;
+           out_msg.Addr := in_msg.Addr;
            out_msg.Type := in_msg.Type;
            out_msg.Requestor := in_msg.Requestor;
            out_msg.RetryNum := in_msg.RetryNum;
@@ -514,7 +514,7 @@ machine(L2Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       // FIXME, should use a 3rd vnet
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Sender := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
@@ -530,7 +530,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     if (cache_entry.Tokens > 0) {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
@@ -544,7 +544,7 @@ machine(L2Cache, "Token protocol")
   action(cc_dirtyReplacement, "\c", desc="Issue dirty writeback") {
     assert(is_valid(cache_entry));
     enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Tokens := cache_entry.Tokens;
@@ -567,7 +567,7 @@ machine(L2Cache, "Token protocol")
       assert(is_valid(cache_entry));
       if (cache_entry.Tokens > (N_tokens + (max_tokens() / 2))) {
         enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_SHARED;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
@@ -580,7 +580,7 @@ machine(L2Cache, "Token protocol")
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:DATA_SHARED;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
@@ -598,7 +598,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -616,7 +616,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     if (cache_entry.Tokens > 0) {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -631,7 +631,7 @@ machine(L2Cache, "Token protocol")
   action(ee_sendDataWithAllTokens, "\e", desc="Send data and all tokens from cache to starver") {
     assert(is_valid(cache_entry));
     enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_OWNER;
       out_msg.Sender := machineID;
       out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -650,7 +650,7 @@ machine(L2Cache, "Token protocol")
     assert(cache_entry.Tokens > 0);
     if (cache_entry.Tokens > 1) {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -667,7 +667,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert(cache_entry.Tokens > (max_tokens() / 2) + 1);
     enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -684,7 +684,7 @@ machine(L2Cache, "Token protocol")
     assert(is_valid(cache_entry));
     assert(cache_entry.Tokens == (max_tokens() / 2) + 1);
     enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -703,7 +703,7 @@ machine(L2Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       // FIXME, should use a 3rd vnet in some cases
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -720,7 +720,7 @@ machine(L2Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       // FIXME, should use a 3rd vnet in some cases
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (in_msg.Type == CoherenceResponseType:WB_SHARED_DATA) {
           out_msg.Type := CoherenceResponseType:DATA_SHARED;
         } else {
@@ -742,7 +742,7 @@ machine(L2Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       // FIXME, should use a 3rd vnet in some cases
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -757,20 +757,20 @@ machine(L2Cache, "Token protocol")
 
   action(h_updateFilterFromL1HintOrWB, "h", desc="update filter from received writeback") {
     peek(responseNetwork_in, ResponseMsg) {
-      removeSharer(in_msg.Address, machineIDToNodeID(in_msg.Sender));
+      removeSharer(in_msg.Addr, machineIDToNodeID(in_msg.Sender));
     }
   }
 
   action(j_forwardTransientRequestToLocalSharers, "j", desc="Forward external transient request to local sharers") {
     peek(requestNetwork_in, RequestMsg) {
-      if (filtering_enabled == true && in_msg.RetryNum == 0 && sharersExist(in_msg.Address) == false) {
+      if (filtering_enabled == true && in_msg.RetryNum == 0 && sharersExist(in_msg.Addr) == false) {
         //profile_filter_action(1);
         DPRINTF(RubySlicc, "filtered message, Retry Num: %d\n",
                 in_msg.RetryNum);
       }
       else {
         enqueue(localRequestNetwork_out, RequestMsg, latency=l2_response_latency ) {
-           out_msg.Address := in_msg.Address;
+           out_msg.Addr := in_msg.Addr;
            out_msg.Requestor := in_msg.Requestor;
 
            //
@@ -797,7 +797,7 @@ machine(L2Cache, "Token protocol")
       assert(cache_entry.Tokens > 0);
       //enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_to_L1_RESPONSE_LATENCY") {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -815,7 +815,7 @@ machine(L2Cache, "Token protocol")
       assert(is_valid(cache_entry));
       assert(cache_entry.Tokens == (max_tokens() / 2) + 1);
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -834,7 +834,7 @@ machine(L2Cache, "Token protocol")
 //      assert(cache_entry.Tokens == max_tokens());
       //enqueue(responseIntraChipL2Network_out, ResponseMsg, latency="L2_to_L1_RESPONSE_LATENCY") {
       enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -883,9 +883,9 @@ machine(L2Cache, "Token protocol")
     peek(L1requestNetwork_in, RequestMsg) {
       if (machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache) {
         if (in_msg.Type == CoherenceRequestType:GETX) {
-          setNewWriter(in_msg.Address, machineIDToNodeID(in_msg.Requestor));
+          setNewWriter(in_msg.Addr, machineIDToNodeID(in_msg.Requestor));
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
-          addNewSharer(in_msg.Address, machineIDToNodeID(in_msg.Requestor));
+          addNewSharer(in_msg.Addr, machineIDToNodeID(in_msg.Requestor));
         }
       }
     }
@@ -909,7 +909,7 @@ machine(L2Cache, "Token protocol")
     if (cache_entry.Tokens > 0) {
       peek(requestNetwork_in, RequestMsg) {
         enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:ACK;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
@@ -927,7 +927,7 @@ machine(L2Cache, "Token protocol")
     if (cache_entry.Tokens > 0) {
       peek(L1requestNetwork_in, RequestMsg) {
         enqueue(responseNetwork_out, ResponseMsg, latency=l2_response_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:ACK;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 5a5fc7259..854e6e2af 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -252,9 +252,9 @@ machine(Directory, "Token protocol")
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -275,32 +275,32 @@ machine(Directory, "Token protocol")
     if (responseNetwork_in.isReady()) {
       peek(responseNetwork_in, ResponseMsg) {
         assert(in_msg.Destination.isElement(machineID));
-        if (getDirectoryEntry(in_msg.Address).Tokens + in_msg.Tokens == max_tokens()) {
+        if (getDirectoryEntry(in_msg.Addr).Tokens + in_msg.Tokens == max_tokens()) {
           if ((in_msg.Type == CoherenceResponseType:DATA_OWNER) ||
               (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
-            trigger(Event:Data_All_Tokens, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Data_All_Tokens, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
-            trigger(Event:Ack_Owner_All_Tokens, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Ack_Owner_All_Tokens, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else if (in_msg.Type == CoherenceResponseType:ACK) {
-            trigger(Event:Ack_All_Tokens, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Ack_All_Tokens, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else {
             DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Invalid message");
           }
         } else {
           if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
-            trigger(Event:Data_Owner, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Data_Owner, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else if ((in_msg.Type == CoherenceResponseType:ACK) ||
                      (in_msg.Type == CoherenceResponseType:DATA_SHARED)) {
-            trigger(Event:Tokens, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Tokens, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else if (in_msg.Type == CoherenceResponseType:ACK_OWNER) {
-            trigger(Event:Ack_Owner, in_msg.Address,
-                    TBEs[in_msg.Address]);
+            trigger(Event:Ack_Owner, in_msg.Addr,
+                    TBEs[in_msg.Addr]);
           } else {
             DPRINTF(RubySlicc, "%s\n", in_msg.Type);
             error("Invalid message");
@@ -318,52 +318,52 @@ machine(Directory, "Token protocol")
         if (distributed_persistent) {
           // Apply the lockdown or unlockdown message to the table
           if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
-            persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Write);
+            persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Write);
           } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
-            persistentTable.persistentRequestLock(in_msg.Address, in_msg.Requestor, AccessType:Read);
+            persistentTable.persistentRequestLock(in_msg.Addr, in_msg.Requestor, AccessType:Read);
           } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
-            persistentTable.persistentRequestUnlock(in_msg.Address, in_msg.Requestor);
+            persistentTable.persistentRequestUnlock(in_msg.Addr, in_msg.Requestor);
           } else {
             error("Invalid message");
           }
 
           // React to the message based on the current state of the table
-          if (persistentTable.isLocked(in_msg.Address)) {
-            if (persistentTable.findSmallest(in_msg.Address) == machineID) {
-              if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
-                trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
-                        TBEs[in_msg.Address]);
+          if (persistentTable.isLocked(in_msg.Addr)) {
+            if (persistentTable.findSmallest(in_msg.Addr) == machineID) {
+              if (getDirectoryEntry(in_msg.Addr).Tokens > 0) {
+                trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Addr,
+                        TBEs[in_msg.Addr]);
               } else {
-                trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
-                        TBEs[in_msg.Address]);
+                trigger(Event:Own_Lock_or_Unlock, in_msg.Addr,
+                        TBEs[in_msg.Addr]);
               }
             } else {
               // locked
-              trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
+              trigger(Event:Lockdown, in_msg.Addr, TBEs[in_msg.Addr]);
             }
           } else {
             // unlocked
-            trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
+            trigger(Event:Unlockdown, in_msg.Addr, TBEs[in_msg.Addr]);
           }
         }
         else {
-          if (persistentTable.findSmallest(in_msg.Address) == machineID) {
-              if (getDirectoryEntry(in_msg.Address).Tokens > 0) {
-                trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Address,
-                        TBEs[in_msg.Address]);
+          if (persistentTable.findSmallest(in_msg.Addr) == machineID) {
+              if (getDirectoryEntry(in_msg.Addr).Tokens > 0) {
+                trigger(Event:Own_Lock_or_Unlock_Tokens, in_msg.Addr,
+                        TBEs[in_msg.Addr]);
               } else {
-                trigger(Event:Own_Lock_or_Unlock, in_msg.Address,
-                        TBEs[in_msg.Address]);
+                trigger(Event:Own_Lock_or_Unlock, in_msg.Addr,
+                        TBEs[in_msg.Addr]);
               }
           } else if (in_msg.Type == PersistentRequestType:GETX_PERSISTENT) {
             // locked
-            trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
+            trigger(Event:Lockdown, in_msg.Addr, TBEs[in_msg.Addr]);
           } else if (in_msg.Type == PersistentRequestType:GETS_PERSISTENT) {
             // locked
-            trigger(Event:Lockdown, in_msg.Address, TBEs[in_msg.Address]);
+            trigger(Event:Lockdown, in_msg.Addr, TBEs[in_msg.Addr]);
           } else if (in_msg.Type == PersistentRequestType:DEACTIVATE_PERSISTENT) {
             // unlocked
-            trigger(Event:Unlockdown, in_msg.Address, TBEs[in_msg.Address]);
+            trigger(Event:Unlockdown, in_msg.Addr, TBEs[in_msg.Addr]);
           } else {
             error("Invalid message");
           }
@@ -377,9 +377,9 @@ machine(Directory, "Token protocol")
       peek(requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:GETS, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:GETS, in_msg.Addr, TBEs[in_msg.Addr]);
         } else if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:GETX, in_msg.Address, TBEs[in_msg.Address]);
+          trigger(Event:GETX, in_msg.Addr, TBEs[in_msg.Addr]);
         } else {
           error("Invalid message");
         }
@@ -415,11 +415,11 @@ machine(Directory, "Token protocol")
       peek(requestNetwork_in, RequestMsg) {
         // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
         enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceResponseType:ACK;
           out_msg.Sender := machineID;
           out_msg.Destination.add(in_msg.Requestor);
-          out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
+          out_msg.Tokens := getDirectoryEntry(in_msg.Addr).Tokens;
           out_msg.MessageSize := MessageSizeType:Response_Control;
         }
       }
@@ -430,7 +430,7 @@ machine(Directory, "Token protocol")
   action(px_tryIssuingPersistentGETXRequest, "px", desc="...") {
     if (okToIssueStarving(address, machineID) && (starving == false)) {
       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := PersistentRequestType:GETX_PERSISTENT;
         out_msg.Requestor := machineID;
         out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -476,7 +476,7 @@ machine(Directory, "Token protocol")
       //
       assert(getDirectoryEntry(address).Tokens != max_tokens());
       enqueue(requestNetwork_out, RequestMsg, latency = "1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := machineID;
 
@@ -500,7 +500,7 @@ machine(Directory, "Token protocol")
   action(ps_tryIssuingPersistentGETSRequest, "ps", desc="...") {
     if (okToIssueStarving(address, machineID) && (starving == false)) {
       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := PersistentRequestType:GETS_PERSISTENT;
         out_msg.Requestor := machineID;
         out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -542,7 +542,7 @@ machine(Directory, "Token protocol")
   action(br_broadcastRead, "br", desc="Broadcast GETS for data") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(requestNetwork_out, RequestMsg, latency = "1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETS;
         out_msg.Requestor := machineID;
 
@@ -568,7 +568,7 @@ machine(Directory, "Token protocol")
     if (getDirectoryEntry(address).Tokens > 0) {
       // enqueue(responseNetwork_out, ResponseMsg, latency="DIRECTORY_CACHE_LATENCY") {// FIXME?
       enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {// FIXME?
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -582,13 +582,13 @@ machine(Directory, "Token protocol")
   action(d_sendMemoryDataWithAllTokens, "d", desc="Send data and tokens to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
         assert(getDirectoryEntry(address).Tokens > 0);
-        out_msg.Tokens := getDirectoryEntry(in_msg.Address).Tokens;
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.Tokens := getDirectoryEntry(in_msg.Addr).Tokens;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         out_msg.Dirty := false;
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
@@ -599,7 +599,7 @@ machine(Directory, "Token protocol")
   action(dd_sendMemDataToStarver, "\d", desc="Send data and tokens to starver") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -615,7 +615,7 @@ machine(Directory, "Token protocol")
 
   action(de_sendTbeDataToStarver, "de", desc="Send data and tokens to starver") {
     enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:DATA_OWNER;
       out_msg.Sender := machineID;
       out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -631,7 +631,7 @@ machine(Directory, "Token protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -644,7 +644,7 @@ machine(Directory, "Token protocol")
 
   action(qp_queueMemoryForPersistent, "qp", desc="Queue off-chip fetch request") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_READ;
       out_msg.Sender := machineID;
       out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
@@ -657,7 +657,7 @@ machine(Directory, "Token protocol")
   action(fd_memoryDma, "fd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -670,7 +670,7 @@ machine(Directory, "Token protocol")
 
   action(lq_queueMemoryWbRequest, "lq", desc="Write data to memory") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
       DPRINTF(RubySlicc, "%s\n", out_msg);
@@ -679,7 +679,7 @@ machine(Directory, "Token protocol")
 
   action(ld_queueMemoryDmaWriteFromTbe, "ld", desc="Write DMA data to memory") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       // first, initialize the data blk to the current version of system memory
       out_msg.DataBlk := tbe.DataBlk;
@@ -691,7 +691,7 @@ machine(Directory, "Token protocol")
 
   action(lr_queueMemoryDmaReadWriteback, "lr", desc="Write DMA data from read to memory") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       // first, initialize the data blk to the current version of system memory
       out_msg.DataBlk := tbe.DataBlk;
@@ -717,7 +717,7 @@ machine(Directory, "Token protocol")
       assert(starving == true);
 
       enqueue(persistentNetwork_out, PersistentMsg, latency = "1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := PersistentRequestType:DEACTIVATE_PERSISTENT;
         out_msg.Requestor := machineID;
         out_msg.Destination.broadcast(MachineType:L1Cache);
@@ -804,22 +804,22 @@ machine(Directory, "Token protocol")
 
   action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
     peek(responseNetwork_in, ResponseMsg) {
-      getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
+      getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
   action(n_checkData, "n", desc="Check incoming clean data message") {
     peek(responseNetwork_in, ResponseMsg) {
-      assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
+      assert(getDirectoryEntry(in_msg.Addr).DataBlk == in_msg.DataBlk);
     }
   }
 
   action(r_bounceResponse, "r", desc="Bounce response to starving processor") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := in_msg.Type;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
@@ -864,18 +864,18 @@ machine(Directory, "Token protocol")
       // implementation.  We include the data in the "dataless"
       // message so we can assert the clean data matches the datablock
       // in memory
-      assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
+      assert(getDirectoryEntry(in_msg.Addr).DataBlk == in_msg.DataBlk);
 
       // Bounce the message, but "re-associate" the data and the owner
       // token.  In essence we're converting an ACK_OWNER message to a
       // DATA_OWNER message, keeping the number of tokens the same.
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_OWNER;
         out_msg.Sender := machineID;
         out_msg.Destination.add(persistentTable.findSmallest(address));
         out_msg.Tokens := in_msg.Tokens;
-        out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
+        out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
         out_msg.Dirty := in_msg.Dirty;
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm
index 6a8d6c6bc..6df417e00 100644
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_token-msg.sm
@@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") {
 
 // PersistentMsg
 structure(PersistentMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   PersistentRequestType Type,  desc="Type of starvation request";
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest Destination,             desc="Destination set";
@@ -79,7 +79,7 @@ structure(PersistentMsg, desc="...", interface="NetworkMessage") {
 
 // RequestMsg
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest Destination,             desc="Multicast destination mask";
@@ -102,7 +102,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
 
 // ResponseMsg
 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceResponseType Type,  desc="Type of response (Ack, Data, etc)";
   MachineID Sender,               desc="Node who sent the data";
   NetDest Destination,             desc="Node to whom the data is sent";
@@ -113,12 +113,12 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
 
   bool functionalRead(Packet *pkt) {
     // No check being carried out on the message type. Would be added later.
-    return testAndRead(Address, DataBlk, pkt);
+    return testAndRead(Addr, DataBlk, pkt);
   }
 
   bool functionalWrite(Packet *pkt) {
     // No check required since all messages are written.
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index df14e690a..8ffa2c2ac 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -329,15 +329,15 @@ machine(L1Cache, "AMD Hammer-like protocol")
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
 
         if (in_msg.Type == TriggerType:L2_to_L1) {
-          trigger(Event:Complete_L2_to_L1, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Complete_L2_to_L1, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_acks, in_msg.Address, cache_entry, tbe);
+          trigger(Event:All_acks, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
-          trigger(Event:All_acks_no_sharers, in_msg.Address, cache_entry, tbe);
+          trigger(Event:All_acks_no_sharers, in_msg.Addr, cache_entry, tbe);
         } else {
           error("Unexpected message");
         }
@@ -350,21 +350,21 @@ machine(L1Cache, "AMD Hammer-like protocol")
   // Response Network
   in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
     if (responseToCache_in.isReady()) {
-      peek(responseToCache_in, ResponseMsg, block_on="Address") {
+      peek(responseToCache_in, ResponseMsg, block_on="Addr") {
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
-          trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Shared_Ack, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-          trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Shared_Data, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Exclusive_Data, in_msg.Addr, cache_entry, tbe);
         } else {
           error("Unexpected message");
         }
@@ -375,38 +375,38 @@ machine(L1Cache, "AMD Hammer-like protocol")
   // Forward Network
   in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
     if (forwardToCache_in.isReady()) {
-      peek(forwardToCache_in, RequestMsg, block_on="Address") {
+      peek(forwardToCache_in, RequestMsg, block_on="Addr") {
 
-        Entry cache_entry := getCacheEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        Entry cache_entry := getCacheEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
 
         if ((in_msg.Type == CoherenceRequestType:GETX) ||
             (in_msg.Type == CoherenceRequestType:GETF)) {
-          trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Other_GETX, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
-          trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Merged_GETS, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:GETS) {
           if (machineCount(MachineType:L1Cache) > 1) {
             if (is_valid(cache_entry)) {
               if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
-                trigger(Event:Other_GETS_No_Mig, in_msg.Address, cache_entry, tbe);
+                trigger(Event:Other_GETS_No_Mig, in_msg.Addr, cache_entry, tbe);
               } else {
-                trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
+                trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe);
               }
             } else {
-              trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
+              trigger(Event:Other_GETS, in_msg.Addr, cache_entry, tbe);
             }
           } else {
-            trigger(Event:NC_DMA_GETS, in_msg.Address, cache_entry, tbe);
+            trigger(Event:NC_DMA_GETS, in_msg.Addr, cache_entry, tbe);
           }
         } else if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Invalidate, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Invalidate, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
-          trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
-          trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) {
-          trigger(Event:Block_Ack, in_msg.Address, cache_entry, tbe);
+          trigger(Event:Block_Ack, in_msg.Addr, cache_entry, tbe);
         } else {
           error("Unexpected message");
         }
@@ -548,7 +548,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(a_issueGETS, "a", desc="Issue GETS") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:GETS;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -563,7 +563,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(b_issueGETX, "b", desc="Issue GETX") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:GETX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -579,7 +579,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     if (machineCount(MachineType:L1Cache) > 1) {
       enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:GETX;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(map_Address_to_Directory(address));
@@ -595,7 +595,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(bf_issueGETF, "bf", desc="Issue GETF") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:GETF;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -611,7 +611,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -634,7 +634,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -655,7 +655,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(d_issuePUT, "d", desc="Issue PUT") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUT;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -665,7 +665,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(df_issuePUTF, "df", desc="Issue PUTF") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:PUTF;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -677,7 +677,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -700,7 +700,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -724,7 +724,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -748,7 +748,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(cache_entry));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination := in_msg.MergedRequestors;
@@ -768,7 +768,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination := in_msg.MergedRequestors;
@@ -787,7 +787,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(f_sendAck, "f", desc="Send ack from cache to requestor") {
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -804,7 +804,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:ACK_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -820,7 +820,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(g_sendUnblock, "g", desc="Send unblock to memory") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCK;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -830,7 +830,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCKM;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -841,7 +841,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceResponseType:UNBLOCKS;
       out_msg.Sender := machineID;
       out_msg.CurOwner := tbe.CurOwner;
@@ -864,7 +864,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(responseToCache_in, ResponseMsg) {
 
       sequencer.readCallback(address,
-                             getNondirectHitMachType(in_msg.Address, in_msg.Sender),
+                             getNondirectHitMachType(in_msg.Addr, in_msg.Sender),
                              cache_entry.DataBlk,
                              tbe.InitialRequestTime,
                              tbe.ForwardRequestTime,
@@ -1015,7 +1015,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
 
   action(ll_L2toL1Transfer, "ll", desc="") {
     enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := TriggerType:L2_to_L1;
     }
   }
@@ -1024,7 +1024,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (tbe.Sharers) {
           out_msg.Type := TriggerType:ALL_ACKS;
         } else {
@@ -1049,7 +1049,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         assert(in_msg.Requestor != machineID);
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -1074,7 +1074,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
         assert(in_msg.Requestor != machineID);
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
@@ -1098,7 +1098,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     peek(forwardToCache_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceResponseType:DATA_SHARED;
         out_msg.Sender := machineID;
         out_msg.Destination := in_msg.MergedRequestors;
@@ -1117,7 +1117,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.Dirty := tbe.Dirty;
@@ -1148,7 +1148,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
   action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
     enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Sender := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
       out_msg.DataBlk := tbe.DataBlk;
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index e1ed2feef..fc9eaa06f 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -305,19 +305,19 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) {
     if (triggerQueue_in.isReady()) {
       peek(triggerQueue_in, TriggerMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == TriggerType:ALL_ACKS) {
-          trigger(Event:All_acks_and_owner_data, in_msg.Address,
+          trigger(Event:All_acks_and_owner_data, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS_OWNER_EXISTS) {
-          trigger(Event:All_acks_and_shared_data, in_msg.Address,
+          trigger(Event:All_acks_and_shared_data, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
-          trigger(Event:All_acks_and_data_no_sharers, in_msg.Address,
+          trigger(Event:All_acks_and_data_no_sharers, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == TriggerType:ALL_UNBLOCKS) {
-          trigger(Event:All_Unblocks, in_msg.Address,
+          trigger(Event:All_Unblocks, in_msg.Addr,
                   pf_entry, tbe);
         } else {
           error("Unexpected message");
@@ -329,23 +329,23 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) {
     if (unblockNetwork_in.isReady()) {
       peek(unblockNetwork_in, ResponseMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
-          trigger(Event:Unblock, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Unblock, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
-          trigger(Event:UnblockS, in_msg.Address, pf_entry, tbe);
+          trigger(Event:UnblockS, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:UNBLOCKM) {
-          trigger(Event:UnblockM, in_msg.Address, pf_entry, tbe);
+          trigger(Event:UnblockM, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_CLEAN) {
-          trigger(Event:Writeback_Clean, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Writeback_Clean, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_DIRTY) {
-          trigger(Event:Writeback_Dirty, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Writeback_Dirty, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_CLEAN) {
-          trigger(Event:Writeback_Exclusive_Clean, in_msg.Address,
+          trigger(Event:Writeback_Exclusive_Clean, in_msg.Addr,
                   pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
-          trigger(Event:Writeback_Exclusive_Dirty, in_msg.Address,
+          trigger(Event:Writeback_Exclusive_Dirty, in_msg.Addr,
                   pf_entry, tbe);
         } else {
           error("Invalid message");
@@ -358,18 +358,18 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) {
     if (responseToDir_in.isReady()) {
       peek(responseToDir_in, ResponseMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Ack, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
-          trigger(Event:Shared_Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Shared_Ack, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
-          trigger(Event:Shared_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Shared_Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Exclusive_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Exclusive_Data, in_msg.Addr, pf_entry, tbe);
         } else {
           error("Unexpected message");
         }
@@ -381,12 +381,12 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(memQueue_in, MemoryMsg, memBuffer, rank=2) {
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Memory_Data, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Address, pf_entry, tbe);
+          trigger(Event:Memory_Ack, in_msg.Addr, pf_entry, tbe);
         } else {
           DPRINTF(RubySlicc, "%d\n", in_msg.Type);
           error("Invalid message");
@@ -398,30 +398,30 @@ machine(Directory, "AMD Hammer-like protocol")
   in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
-        PfEntry pf_entry := getProbeFilterEntry(in_msg.Address);
-        TBE tbe := TBEs[in_msg.Address];
+        PfEntry pf_entry := getProbeFilterEntry(in_msg.Addr);
+        TBE tbe := TBEs[in_msg.Addr];
         if (in_msg.Type == CoherenceRequestType:PUT) {
-          trigger(Event:PUT, in_msg.Address, pf_entry, tbe);
+          trigger(Event:PUT, in_msg.Addr, pf_entry, tbe);
         } else if (in_msg.Type == CoherenceRequestType:PUTF) {
-          trigger(Event:PUTF, in_msg.Address, pf_entry, tbe);
+          trigger(Event:PUTF, in_msg.Addr, pf_entry, tbe);
         } else {
           if (probe_filter_enabled || full_bit_dir_enabled) {
             if (is_valid(pf_entry)) {
-              trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+              trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                       pf_entry, tbe);
             } else {
-              if (probeFilter.cacheAvail(in_msg.Address)) {
-                trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+              if (probeFilter.cacheAvail(in_msg.Addr)) {
+                trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                         pf_entry, tbe);
               } else {
                 trigger(Event:Pf_Replacement,
-                        probeFilter.cacheProbe(in_msg.Address),
-                        getProbeFilterEntry(probeFilter.cacheProbe(in_msg.Address)),
-                        TBEs[probeFilter.cacheProbe(in_msg.Address)]);
+                        probeFilter.cacheProbe(in_msg.Addr),
+                        getProbeFilterEntry(probeFilter.cacheProbe(in_msg.Addr)),
+                        TBEs[probeFilter.cacheProbe(in_msg.Addr)]);
               }
             }
           } else {
-            trigger(cache_request_to_event(in_msg.Type), in_msg.Address,
+            trigger(cache_request_to_event(in_msg.Type), in_msg.Addr,
                     pf_entry, tbe);
           }
         }
@@ -493,7 +493,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_ACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -506,7 +506,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(requestQueue_in, RequestMsg) {
         if (((probe_filter_enabled || full_bit_dir_enabled) && (in_msg.Requestor == cache_entry.Owner)) || machineCount(MachineType:L1Cache) == 1) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:BLOCK_ACK;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.add(in_msg.Requestor);
@@ -519,7 +519,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:WB_NACK;
         out_msg.Requestor := in_msg.Requestor;
         out_msg.Destination.add(in_msg.Requestor);
@@ -678,7 +678,7 @@ machine(Directory, "AMD Hammer-like protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         if (tbe.Sharers) {
           if (tbe.Owned) {
             out_msg.Type := TriggerType:ALL_ACKS_OWNER_EXISTS;
@@ -696,7 +696,7 @@ machine(Directory, "AMD Hammer-like protocol")
     assert(is_valid(tbe));
     if (tbe.NumPendingMsgs == 0) {
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_UNBLOCKS;
       }
     }
@@ -719,7 +719,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs == 0) {
       assert(probe_filter_enabled || full_bit_dir_enabled);
       enqueue(triggerQueue_out, TriggerMsg) {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
       }
     }
@@ -729,7 +729,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency="1") {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := tbe.ResponseType;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -837,7 +837,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestQueue_in, RequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -851,7 +851,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(qd_queueMemoryRequestFromDmaRead, "qd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
       enqueue(memQueue_out, MemoryMsg, latency="1") {
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_READ;
         out_msg.Sender := machineID;
         out_msg.OriginalRequestorMachId := in_msg.Requestor;
@@ -872,7 +872,7 @@ machine(Directory, "AMD Hammer-like protocol")
           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
           if (fwd_set.count() > 0) {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-              out_msg.Address := address;
+              out_msg.Addr := address;
               out_msg.Type := in_msg.Type;
               out_msg.Requestor := in_msg.Requestor;
               out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
@@ -887,7 +887,7 @@ machine(Directory, "AMD Hammer-like protocol")
       } else {
         peek(requestQueue_in, RequestMsg) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := in_msg.Type;
             out_msg.Requestor := in_msg.Requestor;
             out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -907,7 +907,7 @@ machine(Directory, "AMD Hammer-like protocol")
         assert(cache_entry.Sharers.count() > 0);
         peek(requestQueue_in, RequestMsg) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := CoherenceRequestType:INV;
             out_msg.Requestor := machineID;
             out_msg.Destination.setNetDest(MachineType:L1Cache, cache_entry.Sharers);
@@ -916,7 +916,7 @@ machine(Directory, "AMD Hammer-like protocol")
         }
       } else {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:INV;
           out_msg.Requestor := machineID;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -930,7 +930,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (machineCount(MachineType:L1Cache) > 1) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
         assert(is_valid(cache_entry)); 
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
         out_msg.Destination.add(cache_entry.Owner);
@@ -948,7 +948,7 @@ machine(Directory, "AMD Hammer-like protocol")
           fwd_set.remove(machineIDToNodeID(in_msg.Requestor));
           if (fwd_set.count() > 0) {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-                  out_msg.Address := address;
+                  out_msg.Addr := address;
                   out_msg.Type := in_msg.Type;
                   out_msg.Requestor := in_msg.Requestor;
                   out_msg.Destination.setNetDest(MachineType:L1Cache, fwd_set);
@@ -961,7 +961,7 @@ machine(Directory, "AMD Hammer-like protocol")
           }
         } else {
             enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-                out_msg.Address := address;
+                out_msg.Addr := address;
                 out_msg.Type := in_msg.Type;
                 out_msg.Requestor := in_msg.Requestor;
                 out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -975,7 +975,7 @@ machine(Directory, "AMD Hammer-like protocol")
     } else {
       peek(requestQueue_in, RequestMsg) {
           enqueue(responseNetwork_out, ResponseMsg, latency="1") {
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := CoherenceResponseType:ACK;
             out_msg.Sender := machineID;
             out_msg.Destination.add(in_msg.Requestor);
@@ -998,7 +998,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(unblockNetwork_in, ResponseMsg) {
       enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
         assert(is_valid(tbe));
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := CoherenceRequestType:MERGED_GETS;
         out_msg.MergedRequestors := tbe.GetSRequestors;
         if (in_msg.Type == CoherenceResponseType:UNBLOCKS) {
@@ -1019,7 +1019,7 @@ machine(Directory, "AMD Hammer-like protocol")
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
           assert(is_valid(cache_entry)); 
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.add(cache_entry.Owner);
@@ -1032,7 +1032,7 @@ machine(Directory, "AMD Hammer-like protocol")
     } else {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -1053,7 +1053,7 @@ machine(Directory, "AMD Hammer-like protocol")
         if (in_msg.Requestor != cache_entry.Owner) {
           enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
             assert(is_valid(cache_entry));
-            out_msg.Address := address;
+            out_msg.Addr := address;
             out_msg.Type := in_msg.Type;
             out_msg.Requestor := in_msg.Requestor;
             out_msg.Destination.add(cache_entry.Owner);
@@ -1067,7 +1067,7 @@ machine(Directory, "AMD Hammer-like protocol")
      } else {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
           out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches
@@ -1086,7 +1086,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs > 0) {
       peek(dmaRequestQueue_in, DMARequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETX;
           //
           // Send to all L1 caches, since the requestor is the memory controller
@@ -1105,7 +1105,7 @@ machine(Directory, "AMD Hammer-like protocol")
     if (tbe.NumPendingMsgs > 0) {
       peek(dmaRequestQueue_in, DMARequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
-          out_msg.Address := address;
+          out_msg.Addr := address;
           out_msg.Type := CoherenceRequestType:GETS;
           //
           // Send to all L1 caches, since the requestor is the memory controller
@@ -1174,7 +1174,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(responseToDir_in, ResponseMsg) {
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
@@ -1182,7 +1182,7 @@ machine(Directory, "AMD Hammer-like protocol")
     peek(memQueue_in, MemoryMsg) {
       getDirectoryEntry(address).DataBlk := in_msg.DataBlk;
       DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
-              in_msg.Address, in_msg.DataBlk);
+              in_msg.Addr, in_msg.DataBlk);
     }
   }
 
@@ -1247,7 +1247,7 @@ machine(Directory, "AMD Hammer-like protocol")
       enqueue(memQueue_out, MemoryMsg, latency="1") {
         assert(in_msg.Dirty);
         assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
-        out_msg.Address := address;
+        out_msg.Addr := address;
         out_msg.Type := MemoryRequestType:MEMORY_WB;
         out_msg.DataBlk := in_msg.DataBlk;
         DPRINTF(RubySlicc, "%s\n", out_msg);
@@ -1258,7 +1258,7 @@ machine(Directory, "AMD Hammer-like protocol")
   action(ld_queueMemoryDmaWrite, "ld", desc="Write DMA data to memory") {
     enqueue(memQueue_out, MemoryMsg, latency="1") {
       assert(is_valid(tbe));
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := MemoryRequestType:MEMORY_WB;
       // first, initialize the data blk to the current version of system memory
       out_msg.DataBlk := tbe.DataBlk;
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm
index eef78ba45..240b27ed7 100644
--- a/src/mem/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/protocol/MOESI_hammer-msg.sm
@@ -71,7 +71,7 @@ enumeration(TriggerType, desc="...") {
 
 // TriggerMsg
 structure(TriggerMsg, desc="...", interface="Message") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   TriggerType Type,            desc="Type of trigger";
 
   bool functionalRead(Packet *pkt) {
@@ -87,7 +87,7 @@ structure(TriggerMsg, desc="...", interface="Message") {
 
 // RequestMsg (and also forwarded requests)
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest MergedRequestors,    desc="Merge set of read requestors";
@@ -114,7 +114,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
 
 // ResponseMsg (and also unblock requests)
 structure(ResponseMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceResponseType Type,  desc="Type of response (Ack, Data, etc)";
   MachineID Sender,               desc="Node who sent the data";
   MachineID CurOwner,      desc="current owner of the block, used for UnblockS responses";
@@ -138,7 +138,7 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:WB_DIRTY ||
         Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
-        return testAndRead(Address, DataBlk, pkt);
+        return testAndRead(Addr, DataBlk, pkt);
     }
 
     return false;
@@ -148,7 +148,7 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") {
     // Message type does not matter since all messages are written.
     // If a protocol reads data from a packet that is not supposed
     // to hold the data, then the fault lies with the protocol.
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
 
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index 81e648783..54dd8bb94 100644
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -139,7 +139,7 @@ machine(L1Cache, "Network_test L1 Cache")
 
   action(a_issueRequest, "a", desc="Issue a request") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:MSG;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -150,7 +150,7 @@ machine(L1Cache, "Network_test L1 Cache")
 
   action(b_issueForward, "b", desc="Issue a forward") {
     enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:MSG;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -160,7 +160,7 @@ machine(L1Cache, "Network_test L1 Cache")
 
   action(c_issueResponse, "c", desc="Issue a response") {
     enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) {
-      out_msg.Address := address;
+      out_msg.Addr := address;
       out_msg.Type := CoherenceRequestType:MSG;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm
index 57736b66d..47e248dff 100644
--- a/src/mem/protocol/Network_test-dir.sm
+++ b/src/mem/protocol/Network_test-dir.sm
@@ -86,7 +86,7 @@ machine(Directory, "Network_test Directory")
     if (requestQueue_in.isReady()) {
       peek(requestQueue_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:MSG) {
-          trigger(Event:Receive_Request, in_msg.Address);
+          trigger(Event:Receive_Request, in_msg.Addr);
         } else {
           error("Invalid message");
         }
@@ -97,7 +97,7 @@ machine(Directory, "Network_test Directory")
     if (forwardQueue_in.isReady()) {
       peek(forwardQueue_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:MSG) {
-          trigger(Event:Receive_Forward, in_msg.Address);
+          trigger(Event:Receive_Forward, in_msg.Addr);
         } else {
           error("Invalid message");
         }
@@ -108,7 +108,7 @@ machine(Directory, "Network_test Directory")
     if (responseQueue_in.isReady()) {
       peek(responseQueue_in, RequestMsg) {
         if (in_msg.Type == CoherenceRequestType:MSG) {
-          trigger(Event:Receive_Response, in_msg.Address);
+          trigger(Event:Receive_Response, in_msg.Addr);
         } else {
           error("Invalid message");
         }
diff --git a/src/mem/protocol/Network_test-msg.sm b/src/mem/protocol/Network_test-msg.sm
index 672a13db0..d40e74f5f 100644
--- a/src/mem/protocol/Network_test-msg.sm
+++ b/src/mem/protocol/Network_test-msg.sm
@@ -34,7 +34,7 @@ enumeration(CoherenceRequestType, desc="...") {
 
 // RequestMsg (and also forwarded requests)
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
-  Address Address,             desc="Physical address for this request";
+  Address Addr,             desc="Physical address for this request";
   CoherenceRequestType Type,   desc="Type of request (GetS, GetX, PutX, etc)";
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest Destination,             desc="Multicast destination mask";
diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm
index 08bff6e36..21f73828c 100644
--- a/src/mem/protocol/RubySlicc_MemControl.sm
+++ b/src/mem/protocol/RubySlicc_MemControl.sm
@@ -51,7 +51,7 @@ enumeration(MemoryRequestType, desc="...") {
 // Message to and from Memory Control
 
 structure(MemoryMsg, desc="...", interface="Message") {
-  Address Address,              desc="Physical address for this request";
+  Address Addr,              desc="Physical address for this request";
   MemoryRequestType Type,       desc="Type of memory request (MEMORY_READ or MEMORY_WB)";
   MachineID Sender,             desc="What component sent the data";
   MachineID OriginalRequestorMachId, desc="What component originally requested";
@@ -63,10 +63,10 @@ structure(MemoryMsg, desc="...", interface="Message") {
   int Acks,                     desc="How many acks to expect";
 
   bool functionalRead(Packet *pkt) {
-    return testAndRead(Address, DataBlk, pkt);
+    return testAndRead(Addr, DataBlk, pkt);
   }
 
   bool functionalWrite(Packet *pkt) {
-    return testAndWrite(Address, DataBlk, pkt);
+    return testAndWrite(Addr, DataBlk, pkt);
   }
 }
diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc
index 84126a8f5..bf5a8c7ff 100644
--- a/src/mem/ruby/system/RubyMemoryControl.cc
+++ b/src/mem/ruby/system/RubyMemoryControl.cc
@@ -281,7 +281,7 @@ RubyMemoryControl::enqueue(const MsgPtr& message, Cycles latency)
 {
     Cycles arrival_time = curCycle() + latency;
     const MemoryMsg* memMess = safe_cast<const MemoryMsg*>(message.get());
-    physical_address_t addr = memMess->getAddress().getAddress();
+    physical_address_t addr = memMess->getAddr().getAddress();
     MemoryRequestType type = memMess->getType();
     bool is_mem_read = (type == MemoryRequestType_MEMORY_READ);
     MemoryNode thisReq(arrival_time, message, addr, is_mem_read, !is_mem_read);