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authorSteve Reinhardt <stever@gmail.com>2016-01-11 16:20:38 -0500
committerSteve Reinhardt <stever@gmail.com>2016-01-11 16:20:38 -0500
commit8406a54907a00e19389389f0b1497164a7bc637d (patch)
tree60ca61eeac57d7e9c24ab9462a56fb07c18a9adb /src
parent12eb0343784f52994110df7e7fce4a0b639a6ec3 (diff)
downloadgem5-8406a54907a00e19389389f0b1497164a7bc637d.tar.xz
mem: fix bug in packet access endianness changes
The new Packet::setRaw() method incorrectly still contained an htog() conversion. As a result, calls to the old set() method (now defined as setRaw(htog(v))) underwent two htog conversions, which breaks things when htog() is not a no-op. Interestingly the only test that caught this was a SPARC boot test, where an IsaFake device with a non-zero return value was getting swapped twice resulting in a register getting loaded with 0x100000000000000 instead of 1. (Good reason for keeping SPARC around, perhaps?)
Diffstat (limited to 'src')
-rw-r--r--src/mem/packet_access.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 1a2db6921..1fee979ce 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -66,7 +66,7 @@ Packet::setRaw(T v)
{
assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
assert(sizeof(T) <= size);
- *(T*)data = TheISA::htog(v);
+ *(T*)data = v;
}