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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-28 15:30:14 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-28 15:30:14 -0500 |
| commit | a729e4d4b8d59cec891a07d3ba4d0f7d6f0208fe (patch) | |
| tree | 5d97340e75e41d4174d0c217b0fa4cab77ce34f9 /src | |
| parent | f9a341f8e7871135e52d208c65185c96c1e51de5 (diff) | |
| download | gem5-a729e4d4b8d59cec891a07d3ba4d0f7d6f0208fe.tar.xz | |
fix comparing fp registers between legion and m5
make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/sparc/floatregfile.cc | 4 | ||||
| -rw-r--r-- | src/cpu/exetrace.cc | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 1bb78c67b..6f04ca829 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -137,10 +137,12 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) case SingleWidth: result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); + DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32); break; case DoubleWidth: result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); + DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64); break; case QuadWidth: panic("Quad width FP not implemented."); @@ -163,10 +165,12 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) case SingleWidth: result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); + DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32); break; case DoubleWidth: result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); + DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64); break; case QuadWidth: panic("Quad width FP not implemented."); diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 9ea90681c..ea68c7976 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -362,7 +362,7 @@ Trace::InstRecord::dump(ostream &outs) } } for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { - if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { + if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { diffFpRegs = true; } } |