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authorNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:05:55 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:05:55 -0600
commitc120273708ca9843d15f4179c924bccc0f133d65 (patch)
tree253e77e7b35dbd5ea12695952f64e11ceffbfca0 /src
parent9b72a0f627bb9d9f3028e1ad7bf65976863db099 (diff)
downloadgem5-c120273708ca9843d15f4179c924bccc0f133d65.tar.xz
ruby: modify the directed tester to read/write streams
The directed tester supports only generating only read or only write accesses. The patch modifies the tester to support streams that have both read and write accesses.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.py4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc10
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.hh2
3 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index f6a625735..df1205659 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -42,7 +42,9 @@ class SeriesRequestGenerator(DirectedGenerator):
type = 'SeriesRequestGenerator'
cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
- issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
+ num_series = Param.UInt32(1,
+ "number of different address streams to generate")
+ percent_writes = Param.Percent(50, "percent of access that are writes")
class InvalidateGenerator(DirectedGenerator):
type = 'InvalidateGenerator'
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index abcb0278f..f4bb578e3 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -33,13 +33,13 @@
#include "debug/DirectedTest.hh"
SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
- : DirectedGenerator(p)
+ : DirectedGenerator(p),
+ m_addr_increment_size(p->addr_increment_size),
+ m_percent_writes(p->percent_writes)
{
m_status = SeriesRequestGeneratorStatus_Thinking;
m_active_node = 0;
m_address = 0x0;
- m_addr_increment_size = p->addr_increment_size;
- m_issue_writes = p->issue_writes;
}
SeriesRequestGenerator::~SeriesRequestGenerator()
@@ -60,11 +60,13 @@ SeriesRequestGenerator::initiate()
Request *req = new Request(m_address, 1, flags, masterId);
Packet::Command cmd;
- if (m_issue_writes) {
+ bool do_write = ((random() % 100) < m_percent_writes);
+ if (do_write) {
cmd = MemCmd::WriteReq;
} else {
cmd = MemCmd::ReadReq;
}
+
PacketPtr pkt = new Packet(req, cmd);
uint8_t* dummyData = new uint8_t;
*dummyData = 0;
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 9b1c3e8ba..944a179cb 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -56,7 +56,7 @@ class SeriesRequestGenerator : public DirectedGenerator
Addr m_address;
uint32_t m_active_node;
uint32_t m_addr_increment_size;
- bool m_issue_writes;
+ uint32_t m_percent_writes;
};
#endif //__CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__