bus: clean up default responder code.

Clean up some minor things left over from the default responder
change in rev 9af6fb59752f.  Mostly renaming the 'responder_set'
param to 'use_default_range' to actually reflect what it does...
old name wasn't that descriptive in the first place, but now
it really doesn't make sense at all.

Also got rid of the bogus obsolete assignment to 'bus.responder'
which used to be a parameter but now is interpreted as an
implicit child assignment, and which was giving me problems in
the config restructuring to come.  (A good argument for not
allowing implicit child assignments, IMO, but that's water under
the bridge, I'm afraid.)

Also moved the Bus constructor to the .cc file since that's
where it should have been all along.

5 files changed, 47 insertions, 49 deletions

diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index 5440486b6..e6a899604 100644
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -96,8 +96,7 @@ class Tsunami(Platform):
         self.cchip.pio = bus.port
         self.pchip.pio = bus.port
         self.pciconfig.pio = bus.default
-        bus.responder_set = True
-        bus.responder = self.pciconfig
+        bus.use_default_range = True
         self.fake_sm_chip.pio = bus.port
         self.fake_uart1.pio = bus.port
         self.fake_uart2.pio = bus.port
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 6f315cbcb..bb8c91ac6 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -79,5 +79,4 @@ class Pc(Platform):
         self.fake_com_4.pio = bus.port
         self.fake_floppy.pio = bus.port
         self.pciconfig.pio = bus.default
-        bus.responder_set = True
-        bus.responder = self.pciconfig
+        bus.use_default_range = True
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index b3f6b2946..fda91742f 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -31,9 +31,6 @@ from m5.params import *
 from m5.proxy import *
 from MemObject import MemObject
 
-if buildEnv['FULL_SYSTEM']:
-    from Device import BadAddr
-
 class Bus(MemObject):
     type = 'Bus'
     port = VectorPort("vector port for connecting devices")
@@ -41,6 +38,8 @@ class Bus(MemObject):
     clock = Param.Clock("1GHz", "bus clock speed")
     header_cycles = Param.Int(1, "cycles of overhead per transaction")
     width = Param.Int(64, "bus width (bytes)")
-    responder_set = Param.Bool(False, "Did the user specify a default responder.")
     block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
-    default = Port("Default port for requests that aren't handled by a device.")
+    default = \
+            Port("Default port for requests that aren't handled by a device.")
+    use_default_range = \
+            Param.Bool(False, "Query default port device for legal range.")
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index cac08d1a8..39399017c 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -40,6 +40,25 @@
 #include "base/trace.hh"
 #include "mem/bus.hh"
 
+Bus::Bus(const BusParams *p)
+    : MemObject(p), busId(p->bus_id), clock(p->clock),
+      headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
+      drainEvent(NULL), busIdle(this), inRetry(false), maxId(0),
+      defaultPort(NULL), funcPort(NULL), funcPortId(-4),
+      useDefaultRange(p->use_default_range), defaultBlockSize(p->block_size),
+      cachedBlockSize(0), cachedBlockSizeValid(false)
+{
+    //width, clock period, and header cycles must be positive
+    if (width <= 0)
+        fatal("Bus width must be positive\n");
+    if (clock <= 0)
+        fatal("Bus clock period must be positive\n");
+    if (headerCycles <= 0)
+        fatal("Number of header cycles must be positive\n");
+    clearBusCache();
+    clearPortCache();
+}
+
 Port *
 Bus::getPort(const std::string &if_name, int idx)
 {
@@ -310,19 +329,22 @@ int
 Bus::findPort(Addr addr)
 {
     /* An interval tree would be a better way to do this. --ali. */
-    int dest_id = -1;
+    int dest_id;
 
     dest_id = checkPortCache(addr);
-    if (dest_id == -1) {
-        PortIter i = portMap.find(RangeSize(addr,1));
-        if (i != portMap.end()) {
-            dest_id = i->second;
-            updatePortCache(dest_id, i->first.start, i->first.end);
-        }
+    if (dest_id != -1)
+        return dest_id;
+
+    // Check normal port ranges
+    PortIter i = portMap.find(RangeSize(addr,1));
+    if (i != portMap.end()) {
+        dest_id = i->second;
+        updatePortCache(dest_id, i->first.start, i->first.end);
+        return dest_id;
     }
 
     // Check if this matches the default range
-    if (dest_id == -1) {
+    if (useDefaultRange) {
         AddrRangeIter a_end = defaultRange.end();
         for (AddrRangeIter i = defaultRange.begin(); i != a_end; i++) {
             if (*i == addr) {
@@ -331,18 +353,12 @@ Bus::findPort(Addr addr)
             }
         }
 
-        if (responderSet) {
-            panic("Unable to find destination for addr (user set default "
-                  "responder): %#llx\n", addr);
-        } else {
-            DPRINTF(Bus, "Unable to find destination for addr: %#llx, will use "
-                    "default port\n", addr);
-
-            return defaultId;
-        }
+        panic("Unable to find destination for addr %#llx\n", addr);
     }
 
-    return dest_id;
+    DPRINTF(Bus, "Unable to find destination for addr %#llx, "
+            "will use default port\n", addr);
+    return defaultId;
 }
 
 
@@ -484,7 +500,7 @@ Bus::recvStatusChange(Port::Status status, int id)
     if (id == defaultId) {
         defaultRange.clear();
         // Only try to update these ranges if the user set a default responder.
-        if (responderSet) {
+        if (useDefaultRange) {
             defaultPort->getPeerAddressRanges(ranges, snoops);
             assert(snoops == false);
             for(iter = ranges.begin(); iter != ranges.end(); iter++) {
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 97a65c8a9..ba02e3328 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -305,8 +305,11 @@ class Bus : public MemObject
     BusPort *funcPort;
     int funcPortId;
 
-    /** Has the user specified their own default responder? */
-    bool responderSet;
+    /** If true, use address range provided by default device.  Any
+       address not handled by another port and not in default device's
+       range will cause a fatal error.  If false, just send all
+       addresses not handled by another port to default device. */
+    bool useDefaultRange;
 
     unsigned defaultBlockSize;
     unsigned cachedBlockSize;
@@ -371,25 +374,7 @@ class Bus : public MemObject
 
     unsigned int drain(Event *de);
 
-    Bus(const BusParams *p)
-        : MemObject(p), busId(p->bus_id), clock(p->clock),
-          headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
-          drainEvent(NULL), busIdle(this), inRetry(false), maxId(0),
-          defaultPort(NULL), funcPort(NULL), funcPortId(-4),
-          responderSet(p->responder_set), defaultBlockSize(p->block_size),
-          cachedBlockSize(0), cachedBlockSizeValid(false)
-    {
-        //width, clock period, and header cycles must be positive
-        if (width <= 0)
-            fatal("Bus width must be positive\n");
-        if (clock <= 0)
-            fatal("Bus clock period must be positive\n");
-        if (headerCycles <= 0)
-            fatal("Number of header cycles must be positive\n");
-        clearBusCache();
-        clearPortCache();
-    }
-
+    Bus(const BusParams *p);
 };
 
 #endif //__MEM_BUS_HH__