Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.

--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b

23 files changed, 31 insertions, 94 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 314b445e0..dca948bbd 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -147,7 +147,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
 Fault
 SimpleThread::hwrei()
 {
-    if (!inPalMode())
+    if (!(readPC() & 0x3))
         return new UnimplementedOpcodeFault;
 
     setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 7179bf025..5efcf92e4 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -125,7 +125,7 @@ void AlphaFault::invoke(ThreadContext * tc)
     countStat()++;
 
     // exception restart address
-    if (setRestartAddress() || !tc->inPalMode())
+    if (setRestartAddress() || !(tc->readPC() & 0x3))
         tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 2f031f434..75031ae47 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -88,15 +88,6 @@ namespace AlphaISA
             intstatus = 0;
         }
 
-        bool check_interrupt(int int_num) const {
-            if (int_num > NumInterruptLevels)
-                panic("int_num out of bounds\n");
-
-            return interrupts[int_num] != 0;
-        }
-
-        bool check_interrupts() const { return intstatus != 0; }
-
         void serialize(std::ostream &os)
         {
             SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
@@ -109,6 +100,11 @@ namespace AlphaISA
             UNSERIALIZE_SCALAR(intstatus);
         }
 
+        bool check_interrupts(ThreadContext * tc) const
+        {
+            return (intstatus != 0) && !(tc->readPC() & 0x3);
+        }
+
         Fault getInterrupt(ThreadContext * tc)
         {
             int ipl = 0;
@@ -163,7 +159,6 @@ namespace AlphaISA
         }
 
       private:
-        uint64_t intr_status() const { return intstatus; }
     };
 }
 
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 207473d80..79d22c992 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -89,12 +89,8 @@ class BaseCPU : public MemObject
     virtual void clear_interrupts();
     bool checkInterrupts;
 
-    bool check_interrupt(int int_num) const {
-        return interrupts.check_interrupt(int_num);
-    }
-
-    bool check_interrupts() const { return interrupts.check_interrupts(); }
-    //uint64_t intr_status() const { return interrupts.intr_status(); }
+    bool check_interrupts(ThreadContext * tc) const
+    { return interrupts.check_interrupts(tc); }
 
     class ProfileEvent : public Event
     {
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 454f3892b..9be54529f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -327,7 +327,6 @@ class CheckerCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
-    bool inPalMode() { return thread->inPalMode(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index cd399dd22..b46031167 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -271,9 +271,6 @@ class CheckerThreadContext : public ThreadContext
         checkerTC->setStCondFailures(sc_failures);
         actualTC->setStCondFailures(sc_failures);
     }
-#if FULL_SYSTEM
-    bool inPalMode() { return actualTC->inPalMode(); }
-#endif
 
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 01749a2a2..b62550062 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     void post_interrupt(int int_num, int index);
     /** HW return from error interrupt. */
     Fault hwrei(unsigned tid);
-    /** Returns if a specific PC is a PAL mode PC. */
-    bool inPalMode(uint64_t PC)
-    { return AlphaISA::PcPAL(PC); }
 
     bool simPalCheck(int palFunc, unsigned tid);
 
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 170a53c23..750ccc912 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -278,11 +278,12 @@ AlphaO3CPU<Impl>::processInterrupts()
 
     // Check if there are any outstanding interrupts
     //Handle the interrupts
-    this->checkInterrupts = false;
     Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
 
-    if (interrupt != NoFault)
+    if (interrupt != NoFault) {
+        this->checkInterrupts = false;
         this->trap(interrupt, 0);
+    }
 }
 
 #endif // FULL_SYSTEM
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index e711de510..31df8ff78 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
 #if FULL_SYSTEM
     /** Calls hardware return from error interrupt. */
     Fault hwrei();
-    /** Checks if system is in PAL mode. */
-    bool inPalMode();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index f27cd5961..6fc548a85 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -113,7 +113,7 @@ Fault
 AlphaDynInst<Impl>::hwrei()
 {
     // Can only do a hwrei when in pal mode.
-    if (!this->cpu->inPalMode(this->readPC()))
+    if (!(this->readPC() & 0x3))
         return new AlphaISA::UnimplementedOpcodeFault;
 
     // Set the next PC based on the value of the EXC_ADDR IPR.
@@ -128,13 +128,6 @@ AlphaDynInst<Impl>::hwrei()
 }
 
 template <class Impl>
-bool
-AlphaDynInst<Impl>::inPalMode()
-{
-    return this->cpu->inPalMode(this->PC);
-}
-
-template <class Impl>
 void
 AlphaDynInst<Impl>::trap(Fault fault)
 {
diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index f0cecee35..bcecb7087 100644
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext<Impl>
     {
         return this->thread->quiesceEvent;
     }
-
-    /** Returns if the thread is currently in PAL mode, based on
-     * the PC's value. */
-    virtual bool inPalMode()
-    { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); }
 #endif
 
     virtual uint64_t readNextNPC()
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ecf6ed632..bd5c4f9ce 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -638,8 +638,7 @@ DefaultCommit<Impl>::commit()
     // and no other traps or external squashes are currently pending.
     // @todo: Allow other threads to handle interrupts.
     if (cpu->checkInterrupts &&
-        cpu->check_interrupts() &&
-        !cpu->inPalMode(readPC()) &&
+        cpu->check_interrupts(cpu->tcBase(0)) &&
         !trapSquash[0] &&
         !tcSquash[0]) {
         // Tell fetch that there is an interrupt pending.  This will
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 31f3b96d6..4c39341aa 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -559,14 +559,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
 {
     Fault fault = NoFault;
 
-#if FULL_SYSTEM
-    // Flag to say whether or not address is physical addr.
-    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
-#else
-    unsigned flags = 0;
-#endif // FULL_SYSTEM
-
-    if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
+    //AlphaDep
+    if (cacheBlocked || isSwitchedOut() ||
+            (interruptPending && (fetch_PC & 0x3))) {
         // Hold off fetch from getting new instructions when:
         // Cache is blocked, or
         // while an interrupt is pending and we're not in PAL mode, or
@@ -585,7 +580,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     // Setup the memReq to do a read of the first instruction's address.
     // Set the appropriate read size and flags as well.
     // Build request here.
-    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
+    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
                                      fetch_PC, cpu->readCpuId(), tid);
 
     memReq[tid] = mem_req;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 828c2b4ca..b3d3531e9 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -239,10 +239,6 @@ class OzoneCPU : public BaseCPU
         void setStCondFailures(unsigned sc_failures)
         { thread->storeCondFailures = sc_failures; }
 
-#if FULL_SYSTEM
-        bool inPalMode() { return cpu->inPalMode(); }
-#endif
-
         bool misspeculating() { return false; }
 
 #if !FULL_SYSTEM
@@ -584,8 +580,6 @@ class OzoneCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei();
-    bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
-    bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
     bool simPalCheck(int palFunc);
     void processInterrupts();
 #else
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 532317b08..9445a5309 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -238,7 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
 #if FULL_SYSTEM
     Fault hwrei();
-    bool inPalMode();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
 #else
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 68736ae61..426841536 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -249,7 +249,7 @@ template <class Impl>
 Fault
 OzoneDynInst<Impl>::hwrei()
 {
-    if (!this->cpu->inPalMode(this->readPC()))
+    if (!(this->readPC() & 0x3))
         return new AlphaISA::UnimplementedOpcodeFault;
 
     this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
@@ -261,13 +261,6 @@ OzoneDynInst<Impl>::hwrei()
 }
 
 template <class Impl>
-bool
-OzoneDynInst<Impl>::inPalMode()
-{
-    return this->cpu->inPalMode();
-}
-
-template <class Impl>
 void
 OzoneDynInst<Impl>::trap(Fault fault)
 {
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6d02c58cb..73ca6afbe 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -462,15 +462,10 @@ Fault
 FrontEnd<Impl>::fetchCacheLine()
 {
     // Read a cache line, based on the current PC.
-#if FULL_SYSTEM
-    // Flag to say whether or not address is physical addr.
-    unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
-#else
-    unsigned flags = 0;
-#endif // FULL_SYSTEM
     Fault fault = NoFault;
 
-    if (interruptPending && flags == 0) {
+    //AlphaDep
+    if (interruptPending && (PC & 0x3)) {
         return fault;
     }
 
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 8aef9c074..87bf0a7a2 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -152,11 +152,11 @@ InorderBackEnd<Impl>::tick()
 #if FULL_SYSTEM
     if (interruptBlocked ||
         (cpu->checkInterrupts &&
-        cpu->check_interrupts() &&
-        !cpu->inPalMode())) {
+        cpu->check_interrupts(tc))) {
         if (!robEmpty()) {
             interruptBlocked = true;
-        } else if (robEmpty() && cpu->inPalMode()) {
+        //AlphaDep
+        } else if (robEmpty() && (PC & 0x3)) {
             // Will need to let the front end continue a bit until
             // we're out of pal mode.  Hopefully we never get into an
             // infinite loop...
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index c39b9e08b..a181c93f4 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -526,8 +526,7 @@ void
 LWBackEnd<Impl>::checkInterrupts()
 {
     if (cpu->checkInterrupts &&
-        cpu->check_interrupts() &&
-        !cpu->inPalMode(thread->readPC()) &&
+        cpu->check_interrupts(tc) &&
         !trapSquash &&
         !tcSquash) {
         frontEnd->interruptPending = true;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0c7b5eafe..e91569db2 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -311,11 +311,11 @@ void
 BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
-    if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
-        checkInterrupts = false;
+    if (checkInterrupts && check_interrupts(tc)) {
         Fault interrupt = interrupts.getInterrupt(tc);
 
         if (interrupt != NoFault) {
+            checkInterrupts = false;
             interrupt->invoke(tc);
         }
     }
@@ -371,6 +371,10 @@ BaseSimpleCPU::preExecute()
         StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
 #elif THE_ISA == SPARC_ISA
         StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+#elif THE_ISA == MIPS_ISA
+        //Mips doesn't do anything in it's MakeExtMI function right now,
+        //so it won't be called.
+        StaticInstPtr instPtr = StaticInst::decode(inst);
 #endif
         if (instPtr->isMacroOp()) {
             curMacroStaticInst = instPtr;
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index d13be2877..efb884325 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -302,7 +302,6 @@ class BaseSimpleCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
-    bool inPalMode() { return thread->inPalMode(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 9a575f06b..600588295 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -440,10 +440,6 @@ class SimpleThread : public ThreadState
     void setStCondFailures(unsigned sc_failures)
     { storeCondFailures = sc_failures; }
 
-#if FULL_SYSTEM
-    bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
-#endif
-
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index dfc6fbc2a..82d75b161 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -236,10 +236,6 @@ class ThreadContext
 
     virtual void setStCondFailures(unsigned sc_failures) = 0;
 
-#if FULL_SYSTEM
-    virtual bool inPalMode() = 0;
-#endif
-
     // Only really makes sense for old CPU model.  Still could be useful though.
     virtual bool misspeculating() = 0;
 
@@ -424,9 +420,6 @@ class ProxyThreadContext : public ThreadContext
 
     void setStCondFailures(unsigned sc_failures)
     { actualTC->setStCondFailures(sc_failures); }
-#if FULL_SYSTEM
-    bool inPalMode() { return actualTC->inPalMode(); }
-#endif
 
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }