X86: Make the IO ports work using extra physical address lines. Add a serial port.

--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6

2 files changed, 12 insertions, 0 deletions

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 08c621615..2e6ea4a22 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -470,6 +470,16 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
             //overlapping.
             req->setPaddr(regNum * sizeof(MiscReg));
             return NoFault;
+        } else if (prefix == IntAddrPrefixIO) {
+            // TODO If CPL > IOPL or in virtual mode, check the I/O permission
+            // bitmap in the TSS.
+
+            Addr IOPort = vaddr & ~IntAddrPrefixMask;
+            // Make sure the address fits in the expected 16 bit IO address
+            // space.
+            assert(!(IOPort & ~0xFFFF));
+            req->setPaddr(PhysAddrPrefixIO | IOPort);
+            return NoFault;
         } else {
             panic("Access to unrecognized internal address space %#x.\n",
                     prefix);
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index dd9258db0..dc71de500 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -87,6 +87,8 @@ namespace X86ISA
     const Addr IntAddrPrefixCPUID = ULL(0x100000000);
     const Addr IntAddrPrefixMSR = ULL(0x200000000);
     const Addr IntAddrPrefixIO = ULL(0x300000000);
+
+    const Addr PhysAddrPrefixIO = ULL(0x1000000000000000);
 }
 
 #endif //__ARCH_X86_X86TRAITS_HH__