Merge zizzer:/bk/newmem

into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab

15 files changed, 108 insertions, 79 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ec5090eb8..86b8fd2d0 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
         {
             AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
 
-            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
-            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
-            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
-            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
-            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
-            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
-            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
+            retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
+            retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
+            retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
+            retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
+            retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
+            retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
+            retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
         }
         break;
 
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index d289f5785..0c5fe17a7 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/types.hh"
 
-#include <string.h>
+#include <cstring>
 #include <iostream>
 
 class Checkpoint;
@@ -61,7 +61,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(d, sizeof(d)); }
+        { std::memset(d, 0, sizeof(d)); }
     };
 }
 
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 0d65f69e0..dea160992 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/types.hh"
 
 #include <iostream>
-#include <strings.h>
+#include <cstring>
 
 class Checkpoint;
 
@@ -71,7 +71,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(regs, sizeof(regs)); }
+        { std::memset(regs, 0, sizeof(regs)); }
     };
 }
 
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index a350aa05f..773e7d10c 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -192,10 +192,10 @@ output decoder {{
     }
 
     const int AlphaFP::alphaToC99RoundingMode[] = {
-        FE_TOWARDZERO,	// Chopped
-        FE_DOWNWARD,	// Minus_Infinity
-        FE_TONEAREST,	// Normal
-        FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR
+        M5_FE_TOWARDZERO,	// Chopped
+        M5_FE_DOWNWARD,	// Minus_Infinity
+        M5_FE_TONEAREST,	// Normal
+        M5_FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR
     };
 
     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@@ -228,10 +228,10 @@ def template FloatingPointExecute {{
         if (roundingMode == Normal) {
             %(code)s;
         } else {
-            fesetround(getC99RoundingMode(
+            m5_fesetround(getC99RoundingMode(
                            xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
-            fesetround(FE_TONEAREST);
+            m5_fesetround(M5_FE_TONEAREST);
         }
 #else
         if (roundingMode != Normal && !warnedOnRounding) {
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 7665d2d4f..5b0868132 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -109,37 +109,22 @@ def format FpBasic(code, *flags) {{
         fp_code = """
     Fsr |= bits(Fsr,4,0) << 5;
     Fsr = insertBits(Fsr,4,0,0);
-#if defined(__sun) || defined (__OpenBSD__)
-    fp_rnd newrnd = FP_RN;
+    int newrnd = M5_FE_TONEAREST;
     switch (Fsr<31:30>) {
-      case 0: newrnd = FP_RN; break;
-      case 1: newrnd = FP_RZ; break;
-      case 2: newrnd = FP_RP; break;
-      case 3: newrnd = FP_RM; break;
+      case 0: newrnd = M5_FE_TONEAREST; break;
+      case 1: newrnd = M5_FE_TOWARDZERO; break;
+      case 2: newrnd = M5_FE_UPWARD; break;
+      case 3: newrnd = M5_FE_DOWNWARD; break;
     }
-    fp_rnd oldrnd = fpsetround(newrnd);
-#else
-    int newrnd = FE_TONEAREST;
-    switch (Fsr<31:30>) {
-      case 0: newrnd = FE_TONEAREST; break;
-      case 1: newrnd = FE_TOWARDZERO; break;
-      case 2: newrnd = FE_UPWARD; break;
-      case 3: newrnd = FE_DOWNWARD; break;
-    }
-    int oldrnd = fegetround();
-    fesetround(newrnd);
-#endif
+    int oldrnd = m5_fegetround();
+    m5_fesetround(newrnd);
 """
 
         fp_code += code
 
 
         fp_code += """
-#if defined(__sun) || defined (__OpenBSD__)
-    fpsetround(oldrnd);
-#else
-    fesetround(oldrnd);
-#endif
+   m5_fesetround(oldrnd);
 """
         fp_code = filterDoubles(fp_code)
         iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 05e9e8731..e9cd660b5 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -53,22 +53,14 @@ output decoder {{
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
 
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
+#include "base/fenv.hh"
 #include <algorithm>
 
 using namespace SparcISA;
 }};
 
 output exec {{
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
-
-#if defined(__sun) || defined (__OpenBSD__)
-#include <ieeefp.h>
-#endif
+#include "base/fenv.hh"
 
 #if FULL_SYSTEM
 #include "sim/pseudo_inst.hh"
diff --git a/src/base/SConscript b/src/base/SConscript
index 5e4aaafc2..cc9d06a0e 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -57,6 +57,7 @@ Source('circlebuf.cc')
 Source('cprintf.cc')
 Source('crc.cc')
 Source('fast_alloc.cc')
+Source('fenv.c')
 Source('fifo_buffer.cc')
 Source('hostinfo.cc')
 Source('hybrid_pred.cc')
diff --git a/src/base/fenv.c b/src/base/fenv.c
new file mode 100644
index 000000000..269913a60
--- /dev/null
+++ b/src/base/fenv.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <fenv.h>
+
+void m5_fesetround(int rm);
+int m5_fegetround();
+
+static const int m5_round_ops[] =  {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD};
+
+void m5_fesetround(int rm)
+{
+    assert(rm > 0 && rm < 4);
+    fesetround(m5_round_ops[rm]);
+}
+
+int m5_fegetround()
+{
+    int x;
+    int rm = fegetround();
+    for(x = 0; x < 4; x++)
+        if (m5_round_ops[x] == rm)
+            return x;
+    abort();
+    return 0;
+}
+
diff --git a/src/base/fenv.hh b/src/base/fenv.hh
index 013d2f09b..42b383888 100644
--- a/src/base/fenv.hh
+++ b/src/base/fenv.hh
@@ -33,20 +33,21 @@
 
 #include "config/use_fenv.hh"
 
-#if USE_FENV
-
-#include <fenv.h>
+#define M5_FE_DOWNWARD     0
+#define M5_FE_TONEAREST    1
+#define M5_FE_TOWARDZERO   2
+#define M5_FE_UPWARD       3
 
+#if USE_FENV
+extern "C" {
+void m5_fesetround(int rm);
+int m5_fegetround();
+}
 #else
 
 // Dummy definitions to allow code to compile w/o a real <fenv.h>.
-
-#define FE_TONEAREST    0
-#define FE_DOWNWARD     0
-#define FE_UPWARD       0
-#define FE_TOWARDZERO   0
-
-inline int fesetround(int rounding_mode) { return 0; }
+inline void m5_fesetround(int rm) { ; }
+inline int m5_fegetround() {return 0; }
 
 #endif // USE_FENV
 
diff --git a/src/base/random.cc b/src/base/random.cc
index ceab337d9..8a2e3c1c0 100644
--- a/src/base/random.cc
+++ b/src/base/random.cc
@@ -29,9 +29,6 @@
  *          Ali Saidi
  */
 
-#if defined(__sun)
-#include <ieeefp.h>
-#endif
 #ifdef __SUNPRO_CC
 #include <stdlib.h>
 #include <math.h>
@@ -40,6 +37,7 @@
 #include <cstdlib>
 #include <cmath>
 
+#include "base/fenv.hh"
 #include "base/random.hh"
 
 using namespace std;
@@ -61,9 +59,10 @@ m5round(double r)
 {
 #if defined(__sun)
     double val;
-    fp_rnd oldrnd = fpsetround(FP_RN);
+    int oldrnd = m5_fegetround();
+    m5_fesetround(M5_FE_TONEAREST);
     val = rint(r);
-    fpsetround(oldrnd);
+    m5_fesetround(oldrnd);
     return val;
 #else
     return round(r);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2e6a43f9c..a775b66d5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -384,25 +384,25 @@ FullO3CPU<Impl>::fullCPURegStats()
         .name(name() + ".cpi")
         .desc("CPI: Cycles Per Instruction")
         .precision(6);
-    cpi = simTicks / committedInsts;
+    cpi = numCycles / committedInsts;
 
     totalCpi
         .name(name() + ".cpi_total")
         .desc("CPI: Total CPI of All Threads")
         .precision(6);
-    totalCpi = simTicks / totalCommittedInsts;
+    totalCpi = numCycles / totalCommittedInsts;
 
     ipc
         .name(name() + ".ipc")
         .desc("IPC: Instructions Per Cycle")
         .precision(6);
-    ipc =  committedInsts / simTicks;
+    ipc =  committedInsts / numCycles;
 
     totalIpc
         .name(name() + ".ipc_total")
         .desc("IPC: Total IPC of All Threads")
         .precision(6);
-    totalIpc =  totalCommittedInsts / simTicks;
+    totalIpc =  totalCommittedInsts / numCycles;
 
 }
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index f24de20d9..cc33e025d 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -33,6 +33,7 @@
 #define __CPU_O3_LSQ_UNIT_HH__
 
 #include <algorithm>
+#include <cstring>
 #include <map>
 #include <queue>
 
@@ -292,7 +293,7 @@ class LSQUnit {
             : inst(NULL), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** Constructs a store queue entry for a given instruction. */
@@ -300,7 +301,7 @@ class LSQUnit {
             : inst(_inst), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** The store instruction. */
diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/console.cc
index f077efe6c..443f376a5 100644
--- a/src/dev/alpha/console.cc
+++ b/src/dev/alpha/console.cc
@@ -76,7 +76,7 @@ AlphaConsole::AlphaConsole(Params *p)
     alphaAccess->diskOperation = 0;
     alphaAccess->outputChar = 0;
     alphaAccess->inputChar = 0;
-    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
+    std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
 
 }
 
diff --git a/src/python/SConscript b/src/python/SConscript
index e1095eabe..3c5ab4da1 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -103,7 +103,6 @@ SimObject('m5/objects/Process.py')
 SimObject('m5/objects/Repl.py')
 SimObject('m5/objects/Root.py')
 SimObject('m5/objects/Sampler.py')
-SimObject('m5/objects/Scsi.py')
 SimObject('m5/objects/SimConsole.py')
 SimObject('m5/objects/SimpleCPU.py')
 SimObject('m5/objects/SimpleDisk.py')
@@ -114,7 +113,3 @@ SimObject('m5/objects/T1000.py')
 #SimObject('m5/objects/Tru64System.py')
 SimObject('m5/objects/Tsunami.py')
 SimObject('m5/objects/Uart.py')
-
-if env['ALPHA_TLASER']:
-    SimObject('m5/objects/DmaEngine.py')
-    SimObject('m5/objects/Turbolaser.py')
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 55cbb50a9..36bdff45e 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -92,10 +92,9 @@ simulate(Tick num_cycles)
         if (async_event) {
             async_event = false;
             if (async_statdump || async_statreset) {
+                Stats::StatEvent(async_statdump, async_statreset);
                 async_statdump = false;
                 async_statreset = false;
-
-                Stats::StatEvent(async_statdump, async_statreset);
             }
 
             if (async_exit) {