remove hit_latency and make latency do the right thing

set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
    set the latency parameter in terms of a latency
configs/common/FSConfig.py:
    give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
    remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    add caches to tsunami-simple configs

--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1

2 files changed, 3 insertions, 6 deletions

diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 318b57d50..e887f711e 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
     Param<bool> prefetch_cache_check_push;
     Param<bool> prefetch_use_cpu_id;
     Param<bool> prefetch_data_accesses_only;
-    Param<int> hit_latency;
 
 END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
 
@@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false),
-    INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1)
+    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
 END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 
 
@@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
             BUILD_NULL_PREFETCHER(TAGS);                                \
         }                                                               \
         Cache<TAGS, c>::Params params(tags, mq, coh, base_params,       \
-                                      pf, prefetch_access, hit_latency, \
+                                      pf, prefetch_access, latency, \
                                       true,                             \
                                       store_compressed,                 \
                                       adaptive_compression,             \
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 773a11bea..7df5215e4 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -9,7 +9,7 @@ class BaseCache(MemObject):
         "Use an adaptive compression scheme")
     assoc = Param.Int("associativity")
     block_size = Param.Int("block size in bytes")
-    latency = Param.Int("Latency")
+    latency = Param.Latency("Latency")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
     compression_latency = Param.Latency('0ns',
@@ -59,6 +59,5 @@ class BaseCache(MemObject):
          "Use the CPU ID to seperate calculations of prefetches")
     prefetch_data_accesses_only = Param.Bool(False,
          "Only prefetch on data not on instruction accesses")
-    hit_latency = Param.Int(1,"Hit Latency of the cache")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")