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authorAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:07 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:07 -0500
commit319443d42dbed8d6b07b8a2b7a0e565ff5bd8abf (patch)
tree49e9d2efb1b21b93cc825dbcbb2c906cbe71fa31 /src
parentb44e0ce52b894fd4eecc9339e213b7a111c2cc1d (diff)
downloadgem5-319443d42dbed8d6b07b8a2b7a0e565ff5bd8abf.tar.xz
scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
Diffstat (limited to 'src')
-rwxr-xr-xsrc/SConscript8
-rw-r--r--src/arch/arm/isa/formats/misc.isa2
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa4
-rw-r--r--src/arch/mips/isa/formats/control.isa7
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa6
-rw-r--r--src/arch/mips/isa/formats/fp.isa5
-rw-r--r--src/arch/mips/isa/formats/mem.isa5
-rw-r--r--src/arch/mips/isa/formats/mt.isa11
-rw-r--r--src/arch/mips/isa/includes.isa3
-rw-r--r--src/arch/sparc/faults.hh13
-rw-r--r--src/arch/x86/bios/intelmp.hh6
-rw-r--r--src/arch/x86/cpuid.hh2
-rw-r--r--src/arch/x86/interrupts.hh4
-rw-r--r--src/base/debug.cc3
-rw-r--r--src/base/debug.hh14
-rw-r--r--src/base/hostinfo.cc1
-rw-r--r--src/base/hostinfo.hh2
-rw-r--r--src/base/inet.hh1
-rw-r--r--src/base/statistics.cc2
-rw-r--r--src/base/statistics.hh10
-rw-r--r--src/base/stats/text.hh3
-rw-r--r--src/base/userinfo.cc2
-rw-r--r--src/cpu/legiontrace.hh2
-rw-r--r--src/cpu/pc_event.hh5
-rw-r--r--src/dev/disk_image.hh16
-rw-r--r--src/kern/tru64/dump_mbuf.cc1
-rw-r--r--src/kern/tru64/printf.cc1
-rw-r--r--src/mem/ruby/buffers/MessageBuffer.hh2
-rw-r--r--src/mem/ruby/network/simple/PerfectSwitch.hh2
-rw-r--r--src/mem/ruby/profiler/AddressProfiler.hh8
-rw-r--r--src/mem/ruby/system/CacheMemory.hh2
-rw-r--r--src/mem/ruby/system/RubyMemoryControl.hh2
-rw-r--r--src/mem/ruby/system/WireBuffer.hh2
-rw-r--r--src/python/swig/pyobject.cc2
-rw-r--r--src/python/swig/pyobject.hh3
-rw-r--r--src/sim/debug.hh2
-rw-r--r--src/sim/drain.hh3
-rw-r--r--src/sim/eventq.hh2
-rw-r--r--src/sim/init.hh7
-rw-r--r--src/sim/serialize.hh2
-rw-r--r--src/sim/sim_object.hh4
-rw-r--r--src/sim/stat_control.hh6
-rw-r--r--src/sim/system.hh2
43 files changed, 181 insertions, 9 deletions
diff --git a/src/SConscript b/src/SConscript
index 688eb123f..2abe8b2ad 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -899,9 +899,17 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
'-Wno-unused-value'])
if compareVersions(env['GCC_VERSION'], '4.6') >= 0:
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
+
+ # Add additional warnings here that should not be applied to
+ # the SWIG generated code
+ new_env.Append(CXXFLAGS='-Wmissing-declarations')
if env['CLANG']:
swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value'])
+ # Add additional warnings here that should not be applied to
+ # the SWIG generated code
+ new_env.Append(CXXFLAGS='-Wmissing-declarations')
+
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 3865cffe2..00a37d17b 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -81,7 +81,7 @@ def format ArmMsrMrs() {{
let {{
header_output = '''
StaticInstPtr
- decodeMcrMrc15(ExtMachInst machInst);
+ decodeMcrMrc14(ExtMachInst machInst);
'''
decoder_output = '''
StaticInstPtr
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index a32bf6dfc..272f16b17 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -38,7 +38,9 @@
let {{
- header_output = ""
+ header_output = '''
+ uint64_t join32to64(uint32_t r1, uint32_t r0);
+ '''
decoder_output = '''
uint64_t join32to64(uint32_t r1, uint32_t r0)
{
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index d8e5eb111..1480a5589 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -172,6 +172,13 @@ output decoder {{
}};
+output header {{
+ bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
+
+ bool isMMUTLB(%(CPU_exec_context)s *xc);
+
+}};
+
output exec {{
bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index b288b7b20..9dfae3f44 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -135,6 +135,12 @@ def template DspHiLoExecute {{
}
}};
+output header {{
+ bool isDspEnabled(%(CPU_exec_context)s *xc);
+
+ bool isDspPresent(%(CPU_exec_context)s *xc);
+}};
+
//Outputs to decoder.cc
output decoder {{
}};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 63823f404..e6f0258a0 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -86,6 +86,11 @@ output decoder {{
}
}};
+output header {{
+ void fpResetCauseBits(%(CPU_exec_context)s *cpu);
+
+}};
+
output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 0ef2ac6ae..64d000005 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -96,6 +96,11 @@ output decoder {{
}};
+output header {{
+ uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
+
+}};
+
output exec {{
/** return data in cases where there the size of data is only
known in the packet
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 41f94e129..b4d00454e 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -84,6 +84,17 @@ output decoder {{
}
}};
+output header {{
+ void getThrRegExValues(%(CPU_exec_context)s *xc,
+ MipsISA::VPEConf0Reg &vpe_conf0,
+ MipsISA::TCBindReg &tc_bind_mt,
+ MipsISA::TCBindReg &tc_bind,
+ MipsISA::VPEControlReg &vpe_control,
+ MipsISA::MVPConf0Reg &mvp_conf0);
+
+ void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3);
+}};
+
output exec {{
void getThrRegExValues(%(CPU_exec_context)s *xc,
VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index f8c86a71a..9ce1b8810 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -39,7 +39,8 @@ output header {{
#include <sstream>
#include "arch/mips/isa_traits.hh"
-#include "arch/mips/types.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
}};
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 148983f4f..1fee832d3 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -276,6 +276,19 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
+void enterREDState(ThreadContext *tc);
+
+void doREDFault(ThreadContext *tc, TrapType tt);
+
+void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
+
+void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
+
+void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
+
+void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
+ MiscReg TL);
+
} // namespace SparcISA
#endif // __SPARC_FAULTS_HH__
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh
index 909f8ad79..b51d1bd21 100644
--- a/src/arch/x86/bios/intelmp.hh
+++ b/src/arch/x86/bios/intelmp.hh
@@ -73,6 +73,12 @@ struct X86IntelMPAddrSpaceMappingParams;
struct X86IntelMPBusHierarchyParams;
struct X86IntelMPCompatAddrSpaceModParams;
+template<class T>
+uint8_t writeOutField(PortProxy& proxy, Addr addr, T val);
+
+uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
+ int length);
+
namespace X86ISA
{
diff --git a/src/arch/x86/cpuid.hh b/src/arch/x86/cpuid.hh
index 8d3181819..2414cbeb6 100644
--- a/src/arch/x86/cpuid.hh
+++ b/src/arch/x86/cpuid.hh
@@ -55,6 +55,8 @@ namespace X86ISA
{}
};
+ uint64_t stringToRegister(const char *str);
+
bool doCpuid(ThreadContext * tc, uint32_t function,
uint32_t index, CpuidResult &result);
} // namespace X86ISA
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 4e6ef4324..de3eea1a6 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -66,8 +66,12 @@
class ThreadContext;
class BaseCPU;
+int divideFromConf(uint32_t conf);
+
namespace X86ISA {
+ApicRegIndex decodeAddr(Addr paddr);
+
class Interrupts : public BasicPioDevice, IntDev
{
protected:
diff --git a/src/base/debug.cc b/src/base/debug.cc
index ba154f377..2780344a4 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -33,8 +33,6 @@
#include <algorithm>
#include <csignal>
-#include <map>
-#include <vector>
#include "base/cprintf.hh"
#include "base/debug.hh"
@@ -62,7 +60,6 @@ breakpoint()
//
// Flags for debugging purposes. Primarily for trace.hh
//
-typedef std::map<string, Flag *> FlagsMap;
int allFlagsVersion = 0;
FlagsMap &
allFlags()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index d43117e71..589e8fa42 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -32,6 +32,7 @@
#ifndef __BASE_DEBUG_HH__
#define __BASE_DEBUG_HH__
+#include <map>
#include <string>
#include <vector>
@@ -110,6 +111,19 @@ class CompoundFlag : public SimpleFlag
void disable();
};
+typedef std::map<std::string, Flag *> FlagsMap;
+FlagsMap &allFlags();
+
+Flag *findFlag(const std::string &name);
+
+bool changeFlag(const char *s, bool value);
+
} // namespace Debug
+void setDebugFlag(const char *string);
+
+void clearDebugFlag(const char *string);
+
+void dumpDebugFlags();
+
#endif // __BASE_DEBUG_HH__
diff --git a/src/base/hostinfo.cc b/src/base/hostinfo.cc
index 15413de2a..e5a612c46 100644
--- a/src/base/hostinfo.cc
+++ b/src/base/hostinfo.cc
@@ -44,6 +44,7 @@
#include <cstring>
#include <string>
+#include "base/hostinfo.hh"
#include "base/misc.hh"
#include "base/str.hh"
#include "base/types.hh"
diff --git a/src/base/hostinfo.hh b/src/base/hostinfo.hh
index d9a30481a..137af25af 100644
--- a/src/base/hostinfo.hh
+++ b/src/base/hostinfo.hh
@@ -35,6 +35,8 @@
#include "base/types.hh"
+std::string __get_hostname();
+
std::string &hostname();
uint64_t procInfo(const char *filename, const char *target);
diff --git a/src/base/inet.hh b/src/base/inet.hh
index 1df175c1e..4abac7400 100644
--- a/src/base/inet.hh
+++ b/src/base/inet.hh
@@ -463,6 +463,7 @@ class UdpPtr
int pstart() const { return off() + get()->size(); }
};
+uint16_t __tu_cksum(const IpPtr &ip);
uint16_t cksum(const UdpPtr &ptr);
int hsplit(const EthPacketPtr &ptr);
diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 8034625be..630205a59 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -49,7 +49,6 @@ using namespace std;
namespace Stats {
std::string Info::separatorString = "::";
-typedef map<const void *, Info *> MapType;
// We wrap these in a function to make sure they're built in time.
list<Info *> &
@@ -114,7 +113,6 @@ StorageParams::~StorageParams()
{
}
-typedef map<std::string, Info *> NameMapType;
NameMapType &
nameMap()
{
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index c46eedfde..13347b733 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -3164,6 +3164,16 @@ void registerDumpCallback(Callback *cb);
std::list<Info *> &statsList();
+typedef std::map<const void *, Info *> MapType;
+MapType &statsMap();
+
+typedef std::map<std::string, Info *> NameMapType;
+NameMapType &nameMap();
+
+bool validateStatName(const std::string &name);
+
} // namespace Stats
+void debugDumpStats();
+
#endif // __BASE_STATISTICS_HH__
diff --git a/src/base/stats/text.hh b/src/base/stats/text.hh
index 7f7edaa91..8bb290a99 100644
--- a/src/base/stats/text.hh
+++ b/src/base/stats/text.hh
@@ -35,6 +35,7 @@
#include <string>
#include "base/stats/output.hh"
+#include "base/stats/types.hh"
#include "base/output.hh"
namespace Stats {
@@ -75,6 +76,8 @@ class Text : public Output
virtual void end();
};
+std::string ValueToString(Result value, int precision);
+
Output *initText(const std::string &filename, bool desc);
} // namespace Stats
diff --git a/src/base/userinfo.cc b/src/base/userinfo.cc
index 62f7b7b5c..81782012c 100644
--- a/src/base/userinfo.cc
+++ b/src/base/userinfo.cc
@@ -34,6 +34,8 @@
#include <string>
+#include "base/userinfo.hh"
+
std::string
username()
{
diff --git a/src/cpu/legiontrace.hh b/src/cpu/legiontrace.hh
index 24957e40a..84f83d87e 100644
--- a/src/cpu/legiontrace.hh
+++ b/src/cpu/legiontrace.hh
@@ -42,6 +42,8 @@ class ThreadContext;
namespace Trace {
+void setupSharedData();
+
class LegionTraceRecord : public InstRecord
{
public:
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index f26bbf3f2..c73fc3c5a 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -39,6 +39,7 @@
class ThreadContext;
class PCEventQueue;
+class System;
class PCEvent
{
@@ -141,4 +142,8 @@ class BreakPCEvent : public PCEvent
virtual void process(ThreadContext *tc);
};
+void sched_break_pc_sys(System *sys, Addr addr);
+
+void sched_break_pc(Addr addr);
+
#endif // __PC_EVENT_HH__
diff --git a/src/dev/disk_image.hh b/src/dev/disk_image.hh
index 905879248..da96082cb 100644
--- a/src/dev/disk_image.hh
+++ b/src/dev/disk_image.hh
@@ -137,4 +137,20 @@ class CowDiskImage : public DiskImage
virtual std::streampos write(const uint8_t *data, std::streampos offset);
};
+void SafeRead(std::ifstream &stream, void *data, int count);
+
+template<class T>
+void SafeRead(std::ifstream &stream, T &data);
+
+template<class T>
+void SafeReadSwap(std::ifstream &stream, T &data);
+
+void SafeWrite(std::ofstream &stream, const void *data, int count);
+
+template<class T>
+void SafeWrite(std::ofstream &stream, const T &data);
+
+template<class T>
+void SafeWriteSwap(std::ofstream &stream, const T &data);
+
#endif // __DISK_IMAGE_HH__
diff --git a/src/kern/tru64/dump_mbuf.cc b/src/kern/tru64/dump_mbuf.cc
index fda1753d3..1eef26c07 100644
--- a/src/kern/tru64/dump_mbuf.cc
+++ b/src/kern/tru64/dump_mbuf.cc
@@ -40,6 +40,7 @@
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "kern/tru64/dump_mbuf.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/arguments.hh"
#include "sim/system.hh"
diff --git a/src/kern/tru64/printf.cc b/src/kern/tru64/printf.cc
index dfd300c12..914a6ae86 100644
--- a/src/kern/tru64/printf.cc
+++ b/src/kern/tru64/printf.cc
@@ -36,6 +36,7 @@
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/types.hh"
+#include "kern/tru64/printf.hh"
#include "sim/arguments.hh"
using namespace std;
diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh
index 74023a8ac..2a52d2a2e 100644
--- a/src/mem/ruby/buffers/MessageBuffer.hh
+++ b/src/mem/ruby/buffers/MessageBuffer.hh
@@ -216,6 +216,8 @@ class MessageBuffer
int m_vnet_id;
};
+Cycles random_time();
+
inline std::ostream&
operator<<(std::ostream& out, const MessageBuffer& obj)
{
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh
index 695c848bc..2f914f39b 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -53,6 +53,8 @@ struct LinkOrder
int m_value;
};
+bool operator<(const LinkOrder& l1, const LinkOrder& l2);
+
class PerfectSwitch : public Consumer
{
public:
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 5bce34bbb..642b5a41a 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -92,6 +92,14 @@ class AddressProfiler
int m_num_of_sequencers;
};
+AccessTraceForAddress& lookupTraceForAddress(const Address& addr,
+ AddressProfiler::AddressMap&
+ record_map);
+
+void printSorted(std::ostream& out, int num_of_sequencers,
+ const AddressProfiler::AddressMap &record_map,
+ std::string description);
+
inline std::ostream&
operator<<(std::ostream& out, const AddressProfiler& obj)
{
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 6b436082f..8aca250b3 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -170,4 +170,6 @@ class CacheMemory : public SimObject
bool m_resource_stalls;
};
+std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
+
#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh
index 68ef054e3..d0dfa5b8d 100644
--- a/src/mem/ruby/system/RubyMemoryControl.hh
+++ b/src/mem/ruby/system/RubyMemoryControl.hh
@@ -168,4 +168,6 @@ class RubyMemoryControl : public MemoryControl
MemCntrlProfiler* m_profiler_ptr;
};
+std::ostream& operator<<(std::ostream& out, const RubyMemoryControl& obj);
+
#endif // __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh
index d71bf4520..3a8804798 100644
--- a/src/mem/ruby/system/WireBuffer.hh
+++ b/src/mem/ruby/system/WireBuffer.hh
@@ -100,4 +100,6 @@ class WireBuffer : public SimObject
};
+std::ostream& operator<<(std::ostream& out, const WireBuffer& obj);
+
#endif // __MEM_RUBY_SYSTEM_WireBuffer_HH__
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
index fc4435781..f534623f8 100644
--- a/src/python/swig/pyobject.cc
+++ b/src/python/swig/pyobject.cc
@@ -35,10 +35,10 @@
#include "base/inifile.hh"
#include "base/output.hh"
#include "dev/etherdevice.hh"
-#include "dev/etherint.hh"
#include "dev/etherobject.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
+#include "python/swig/pyobject.hh"
#include "sim/full_system.hh"
#include "sim/sim_object.hh"
diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh
index ab22df864..8debcc82c 100644
--- a/src/python/swig/pyobject.hh
+++ b/src/python/swig/pyobject.hh
@@ -31,12 +31,15 @@
#include <Python.h>
#include "base/types.hh"
+#include "dev/etherint.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
SimObject *resolveSimObject(const std::string &name);
+EtherInt * lookupEthPort(SimObject *so, const std::string &name, int i);
+
/**
* Connect the described MemObject ports. Called from Python via SWIG.
*/
diff --git a/src/sim/debug.hh b/src/sim/debug.hh
index 0bec5ecf3..bc1bb1e62 100644
--- a/src/sim/debug.hh
+++ b/src/sim/debug.hh
@@ -53,6 +53,8 @@ void takeCheckpoint(Tick when);
*/
void eventqDump();
+void py_interact();
+
int getRemoteGDBPort();
// Remote gdb base port. 0 disables remote gdb.
void setRemoteGDBPort(int port);
diff --git a/src/sim/drain.hh b/src/sim/drain.hh
index 2f5d2d965..6f0769f34 100644
--- a/src/sim/drain.hh
+++ b/src/sim/drain.hh
@@ -236,4 +236,7 @@ class Drainable
};
+DrainManager *createDrainManager();
+void cleanupDrainManager(DrainManager *drain_manager);
+
#endif
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 968be6ca1..80086ccef 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -418,6 +418,8 @@ class EventQueue : public Serializable
#endif
};
+void dumpMainQueue();
+
#ifndef SWIG
class EventManager
{
diff --git a/src/sim/init.hh b/src/sim/init.hh
index ee40b9790..325fc8e6f 100644
--- a/src/sim/init.hh
+++ b/src/sim/init.hh
@@ -31,6 +31,8 @@
#ifndef __SIM_INIT_HH__
#define __SIM_INIT_HH__
+#include <Python.h>
+
/*
* Data structure describing an embedded python file.
*/
@@ -74,8 +76,13 @@ struct EmbeddedSwig
static void initAll();
};
+void dumpStatsHandler(int sigtype);
+void dumprstStatsHandler(int sigtype);
+void exitNowHandler(int sigtype);
+void abortHandler(int sigtype);
void initSignals();
int initM5Python();
int m5Main(int argc, char **argv);
+PyMODINIT_FUNC initm5(void);
#endif // __SIM_INIT_HH__
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index dd33ae74f..e523e68a5 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -178,6 +178,8 @@ class Serializable
static void unserializeGlobals(Checkpoint *cp);
};
+void debug_serialize(const std::string &cpt_dir);
+
//
// A SerializableBuilder serves as an evaluation context for a set of
// parameters that describe a specific instance of a Serializable. This
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index 6424f631b..1cb06d777 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -176,4 +176,8 @@ class SimObject : public EventManager, public Serializable, public Drainable
static SimObject *find(const char *name);
};
+#ifdef DEBUG
+void debugObjectBreak(const char *objs);
+#endif
+
#endif // __SIM_OBJECT_HH__
diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh
index 1a0fcb35b..889a98364 100644
--- a/src/sim/stat_control.hh
+++ b/src/sim/stat_control.hh
@@ -46,6 +46,12 @@
namespace Stats {
+double statElapsedTime();
+
+Tick statElapsedTicks();
+
+Tick statFinalTick();
+
void initSimStats();
/**
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 05b1f2077..38db86cb2 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -472,4 +472,6 @@ class System : public MemObject
};
+void printSystems();
+
#endif // __SYSTEM_HH__