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authorGabe Black <gblack@eecs.umich.edu>2007-07-30 15:38:40 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-30 15:38:40 -0700
commit65db30992c2462624b69fb1b1e737e0e84f9457d (patch)
treede3c1afe87d46b7e9464c3fc2fb96d1dfadbb6c0 /src
parent9536120845bcd3b807e942d42364952ce0d3d090 (diff)
downloadgem5-65db30992c2462624b69fb1b1e737e0e84f9457d.tar.xz
X86: Take into account the regular registers and the microcode registers when decided whether or not to fold.
--HG-- extra : convert_revision : 26feec984dec61799c4afb03a4503a53c35872c5
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/operands.isa12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 127e1b98a..eaedbdf17 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,12 +96,12 @@ def operand_types {{
}};
def operands {{
- 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
- 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
- 'Base': ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3),
- 'Index': ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4),
- 'DestReg': ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
- 'Data': ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
+ 'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0x1C) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
+ 'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0x1C) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
+ 'Index': ('IntReg', 'uqw', '(((index & 0x1C) == 4 ? foldABit : 0) | index)', 'IsInteger', 3),
+ 'Base': ('IntReg', 'uqw', '(((base & 0x1C) == 4 ? foldABit : 0) | base)', 'IsInteger', 4),
+ 'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
+ 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),