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authorSteve Reinhardt <steve.reinhardt@amd.com>2011-05-23 14:29:23 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2011-05-23 14:29:23 -0700
commit19bb896bfeffc0b49197f5b2d8395a6ee4c5e94d (patch)
treea5d4872845cfe0ebb67f95c39729047461966738 /src
parent8a652f9871f9f29279958137e960c8e4a5d1c1f4 (diff)
downloadgem5-19bb896bfeffc0b49197f5b2d8395a6ee4c5e94d.tar.xz
config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/bios/E820.py2
-rw-r--r--src/dev/x86/SouthBridge.py29
2 files changed, 11 insertions, 20 deletions
diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py
index 4e0b699bb..78b5faee0 100644
--- a/src/arch/x86/bios/E820.py
+++ b/src/arch/x86/bios/E820.py
@@ -50,4 +50,4 @@ class X86E820Table(SimObject):
type = 'X86E820Table'
cxx_class = 'X86ISA::E820Table'
- entries = VectorParam.X86E820Entry([], 'entries for the e820 table')
+ entries = VectorParam.X86E820Entry('entries for the e820 table')
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 2d1827998..c23ecf01c 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -57,9 +57,6 @@ class SouthBridge(SimObject):
_pit = I8254(pio_addr=x86IOAddress(0x40))
_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AA(pio_addr=0xFEC00000)
- # This is to make sure the interrupt lines are instantiated. Don't use
- # it for anything directly.
- int_lines = VectorParam.X86IntLine([], "Interrupt lines")
pic1 = Param.I8259(_pic1, "Master PIC")
pic2 = Param.I8259(_pic2, "Slave PIC")
@@ -70,9 +67,6 @@ class SouthBridge(SimObject):
speaker = Param.PcSpeaker(_speaker, "PC speaker")
io_apic = Param.I82094AA(_io_apic, "I/O APIC")
- def connectPins(self, source, sink):
- self.int_lines.append(X86IntLine(source=source, sink=sink))
-
# IDE controller
ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
ide.BAR0 = 0x1f0
@@ -93,19 +87,16 @@ class SouthBridge(SimObject):
def attachIO(self, bus):
# Route interupt signals
- self.connectPins(self.pic1.output, self.io_apic.pin(0))
- self.connectPins(self.pic2.output, self.pic1.pin(2))
- self.connectPins(self.cmos.int_pin, self.pic2.pin(0))
- self.connectPins(self.pit.int_pin, self.pic1.pin(0))
- self.connectPins(self.pit.int_pin, self.io_apic.pin(2))
-# self.connectPins(self.keyboard.keyboard_int_pin,
-# self.pic1.pin(1))
- self.connectPins(self.keyboard.keyboard_int_pin,
- self.io_apic.pin(1))
-# self.connectPins(self.keyboard.mouse_int_pin,
-# self.pic2.pin(4))
- self.connectPins(self.keyboard.mouse_int_pin,
- self.io_apic.pin(12))
+ self.int_lines = \
+ [X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
+ X86IntLine(source=self.pic2.output, sink=self.pic1.pin(2)),
+ X86IntLine(source=self.cmos.int_pin, sink=self.pic2.pin(0)),
+ X86IntLine(source=self.pit.int_pin, sink=self.pic1.pin(0)),
+ X86IntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
+ X86IntLine(source=self.keyboard.keyboard_int_pin,
+ sink=self.io_apic.pin(1)),
+ X86IntLine(source=self.keyboard.mouse_int_pin,
+ sink=self.io_apic.pin(12))]
# Tell the devices about each other
self.pic1.slave = self.pic2
self.speaker.i8254 = self.pit