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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
commit1f059541d6160931b3bb80bef842c45c2521d642 (patch)
tree4e4672300be214e5bba318d77cb917e32f69d672 /src
parent6976b4890a307a2d8584b4e512e3f6d728e59ad5 (diff)
downloadgem5-1f059541d6160931b3bb80bef842c45c2521d642.tar.xz
ARM: Add a new RegImmOp base class.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/insts/misc.cc10
-rw-r--r--src/arch/arm/insts/misc.hh14
-rw-r--r--src/arch/arm/isa/templates/misc.isa20
3 files changed, 44 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index a5a4e3b32..0eae37de0 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -153,6 +153,16 @@ ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 53281400e..6d78b311a 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -107,6 +107,20 @@ class ImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ uint64_t imm;
+
+ RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, uint64_t _imm) :
+ PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegRegOp : public PredOp
{
protected:
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 6f782ba58..87c6e430c 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -118,6 +118,26 @@ def template ImmOpConstructor {{
}
}};
+def template RegImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template RegImmOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{