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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:17:02 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:17:02 -0800
commit2f31643db52927d5c2e06d14e21846f1137d915a (patch)
tree3e3f58e81cf91a49ce376262dd4ce5ddb073dd7d /src
parent7b1cb74ac3c2b9a2a22f64ed88bd60fb353c76d7 (diff)
downloadgem5-2f31643db52927d5c2e06d14e21846f1137d915a.tar.xz
X86: Add a check to chks to verify a task state segment descriptor.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/microasm.isa2
-rw-r--r--src/arch/x86/isa/microops/regop.isa11
2 files changed, 11 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 354ee089e..d1025b137 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -87,7 +87,7 @@ let {{
# Add in symbols for the various checks of segment selectors.
for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
"SoftIntGateCheck", "SSCheck", "IretCheck", "IntCSCheck",
- "TRCheck"):
+ "TRCheck", "TSSCheck"):
assembler.symbols[check] = "Seg%s" % check
for reg in ("TR", "IDTR"):
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 9fb8b2f92..0d569d403 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -235,7 +235,7 @@ output header {{
enum SegmentSelectorCheck {
SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
- SegTRCheck
+ SegTRCheck, SegTSSCheck
};
enum LongModeDescriptorType {
@@ -1124,6 +1124,15 @@ let {{
fault = new GeneralProtection(selector);
}
break;
+ case SegTSSCheck:
+ if (!desc.p) {
+ fault = new SegmentNotPresent(selector);
+ } else if (!(desc.type == 0x9 ||
+ (desc.type == 1 &&
+ m5reg.mode != LongMode))) {
+
+ }
+ break;
default:
panic("Undefined segment check type.\\n");
}