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authorGabe Black <gblack@eecs.umich.edu>2006-12-16 07:22:19 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-16 07:22:19 -0500
commit4d66ddbe35252d3d70a0c3d25d100672db5f1ef9 (patch)
treebd989d141043aa01d1d10b7093a60e468fa365b0 /src
parent181f4f32f6a2ffd19700e54cd5581fce19ec04a5 (diff)
downloadgem5-4d66ddbe35252d3d70a0c3d25d100672db5f1ef9.tar.xz
Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not.
--HG-- extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
Diffstat (limited to 'src')
-rw-r--r--src/cpu/base_dyn_inst.hh47
-rw-r--r--src/cpu/base_dyn_inst_impl.hh6
2 files changed, 36 insertions, 17 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 17e121dbf..40e780695 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -221,6 +221,12 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Predicted next PC. */
Addr predPC;
+ /** Predicted next NPC. */
+ Addr predNPC;
+
+ /** If this is a branch that was predicted taken */
+ bool predTaken;
+
/** Count of total number of dynamic instructions. */
static int instcount;
@@ -336,10 +342,12 @@ class BaseDynInst : public FastAlloc, public RefCounted
* @param inst The binary instruction.
* @param PC The PC of the instruction.
* @param pred_PC The predicted next PC.
+ * @param pred_NPC The predicted next NPC.
* @param seq_num The sequence number of the instruction.
* @param cpu Pointer to the instruction's CPU.
*/
- BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC,
+ BaseDynInst(TheISA::ExtMachInst inst, Addr PC,
+ Addr pred_PC, Addr pred_NPC,
InstSeqNum seq_num, ImplCPU *cpu);
/** BaseDynInst constructor given a StaticInst pointer.
@@ -385,26 +393,35 @@ class BaseDynInst : public FastAlloc, public RefCounted
Addr readNextNPC() { return nextNPC; }
/** Set the predicted target of this current instruction. */
- void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
+ void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
+ {
+ predPC = predicted_PC;
+ predNPC = predicted_NPC;
+ }
+
+ /** Returns the predicted PC immediately after the branch. */
+ Addr readPredPC() { return predPC; }
- /** Returns the predicted target of the branch. */
- Addr readPredTarg() { return predPC; }
+ /** Returns the predicted PC two instructions after the branch */
+ Addr readPredNPC() { return predNPC; }
/** Returns whether the instruction was predicted taken or not. */
- bool predTaken()
-#if ISA_HAS_DELAY_SLOT
- { return predPC != (nextPC + sizeof(TheISA::MachInst)); }
-#else
- { return predPC != (PC + sizeof(TheISA::MachInst)); }
-#endif
+ bool readPredTaken()
+ {
+ return predTaken;
+ }
+
+ void setPredTaken(bool predicted_taken)
+ {
+ predTaken = predicted_taken;
+ }
/** Returns whether the instruction mispredicted. */
bool mispredicted()
-#if ISA_HAS_DELAY_SLOT
- { return predPC != nextNPC; }
-#else
- { return predPC != nextPC; }
-#endif
+ {
+ return predPC != nextPC || predNPC != nextNPC;
+ }
+
//
// Instruction types. Forward checks to StaticInst object.
//
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 2f6859de2..d47384871 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -63,8 +63,8 @@ my_hash_t thishash;
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
- Addr pred_PC, InstSeqNum seq_num,
- ImplCPU *cpu)
+ Addr pred_PC, Addr pred_NPC,
+ InstSeqNum seq_num, ImplCPU *cpu)
: staticInst(machInst), traceData(NULL), cpu(cpu)
{
seqNum = seq_num;
@@ -73,6 +73,8 @@ BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
nextPC = PC + sizeof(TheISA::MachInst);
nextNPC = nextPC + sizeof(TheISA::MachInst);
predPC = pred_PC;
+ predNPC = pred_NPC;
+ predTaken = false;
initVars();
}