diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | 625a43e7c7c4f0bb4fde66cd07a1b74fa3bd1eb0 (patch) | |
| tree | 6dd55fecd4ceba6016de60eef0f7ecdcb08bf416 /src | |
| parent | 6c1b10043fd7c79e1beaae8dd52b93c12fdec42c (diff) | |
| download | gem5-625a43e7c7c4f0bb4fde66cd07a1b74fa3bd1eb0.tar.xz | |
ARM: Implement the mrc and mcr instructions.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 80f55e6ec..42dea7b95 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -500,4 +500,18 @@ let {{ header_output += RegRegImmImmOpDeclare.subst(bfiIop) decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) exec_output += PredOpExecute.subst(bfiIop) + + mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc15Iop) + decoder_output += RegRegOpConstructor.subst(mrc15Iop) + exec_output += PredOpExecute.subst(mrc15Iop) + + mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", + { "code": "MiscDest = Op1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mcr15Iop) + decoder_output += RegRegOpConstructor.subst(mcr15Iop) + exec_output += PredOpExecute.subst(mcr15Iop) }}; |