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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:21:08 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:21:08 -0800
commit68300cfb8c6099cc84cb3e544950c0e6a154ff07 (patch)
tree7679573d037da9c8e74b43554c8acc5aa451b708 /src
parent9842f1ca9d3de48d6bc990248be14b119dca9891 (diff)
downloadgem5-68300cfb8c6099cc84cb3e544950c0e6a154ff07.tar.xz
X86: Make rdcr use merge and the mov to control register instructions use the right operand size.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py2
-rw-r--r--src/arch/x86/isa/microops/regop.isa2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index abe44ae59..dded94968 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -192,10 +192,12 @@ def macroop MOVZX_W_R_P {
};
def macroop MOV_C_R {
+ .adjust_env maxOsz
wrcr reg, regm
};
def macroop MOV_R_C {
+ .adjust_env maxOsz
rdcr reg, regm
};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 1349a64c2..7c2feb398 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -967,7 +967,7 @@ let {{
if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
fault = new InvalidOpcode();
} else {
- DestReg = ControlSrc1;
+ DestReg = merge(DestReg, ControlSrc1, dataSize);
}
'''