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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-07 16:02:22 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-07 16:02:22 -0400 |
commit | 7811500eefc57d8f9f00845b9187d9a1a6ef6655 (patch) | |
tree | 444ff9d2bffdb6ea318248066d256d740ac20d92 /src | |
parent | 76c110d924d2adfa209ad4302af791dfe6f67946 (diff) | |
download | gem5-7811500eefc57d8f9f00845b9187d9a1a6ef6655.tar.xz |
Fix address range calculation. Still need bus to handle snoop ranges.
On the way towards multi-level caches (L2)
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Fix address range calculation. Still need bus to handle snoop ranges.
--HG--
extra : convert_revision : 800078d88aab5e563f4a9bb599f91cd44f36e625
Diffstat (limited to 'src')
-rw-r--r-- | src/mem/cache/base_cache.cc | 10 | ||||
-rw-r--r-- | src/mem/cache/base_cache.hh | 29 |
2 files changed, 34 insertions, 5 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index b2caca765..be9769fdc 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -59,7 +59,7 @@ void BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { - cache->getAddressRanges(resp, snoop); + cache->getAddressRanges(resp, snoop, isCpuSide); } int @@ -167,6 +167,14 @@ BaseCache::getPort(const std::string &if_name, int idx) } void +BaseCache::init() +{ + if (!cpuSidePort || !memSidePort) + panic("Cache not hooked up on both sides\n"); + cpuSidePort->sendStatusChange(Port::RangeChange); +} + +void BaseCache::regStats() { Request temp_req((Addr) NULL, 4, 0); diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index f832735db..0d1bfdfdb 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -143,9 +143,19 @@ class BaseCache : public MemObject fatal("No implementation"); } - virtual void recvStatusChange(Port::Status status, bool isCpuSide) + void recvStatusChange(Port::Status status, bool isCpuSide) { - fatal("No implementation"); + if (status == Port::RangeChange) + { + if (!isCpuSide) + { + cpuSidePort->sendStatusChange(Port::RangeChange); + } + else + { + memSidePort->sendStatusChange(Port::RangeChange); + } + } } virtual Packet *getPacket() @@ -320,6 +330,8 @@ class BaseCache : public MemObject memSidePort = NULL; } + virtual void init(); + /** * Query block size of a cache. * @return The block size @@ -519,9 +531,18 @@ class BaseCache : public MemObject */ void rangeChange() {} - void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) + void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide) { - panic("Unimplimented\n"); + if (isCpuSide) + { + AddrRangeList dummy; + memSidePort->getPeerAddressRanges(resp, dummy); + } + else + { + //This is where snoops get updated + return; + } } }; |