diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
commit | 893533a1264bb369b47f74493adf30ce22829f34 (patch) | |
tree | 07c750519f5ac1b972be47a0ca6f68ee517d9f07 /src | |
parent | a262908acc0a641700a03fcea89c48133f0467cd (diff) | |
download | gem5-893533a1264bb369b47f74493adf30ce22829f34.tar.xz |
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Diffstat (limited to 'src')
-rw-r--r-- | src/mem/cache/BaseCache.py | 1 | ||||
-rw-r--r-- | src/mem/cache/base.cc | 1 | ||||
-rw-r--r-- | src/mem/cache/base.hh | 10 | ||||
-rw-r--r-- | src/mem/cache/cache_impl.hh | 21 |
4 files changed, 32 insertions, 1 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index fdb41bf75..4d6766456 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -65,6 +65,7 @@ class BaseCache(MemObject): forward_snoops = Param.Bool(True, "Forward snoops from mem side to cpu side") is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") + is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") prefetch_on_access = Param.Bool(False, diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index c2068496c..af504d9bc 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -79,6 +79,7 @@ BaseCache::BaseCache(const Params *p) numTarget(p->tgts_per_mshr), forwardSnoops(p->forward_snoops), isTopLevel(p->is_top_level), + isReadOnly(p->is_read_only), blocked(0), order(0), noTargetMSHR(NULL), diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index aaf0ea691..d2cb11f33 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -310,6 +310,14 @@ class BaseCache : public MemObject const bool isTopLevel; /** + * Is this cache read only, for example the instruction cache, or + * table-walker cache. A cache that is read only should never see + * any writes, and should never get any dirty data (and hence + * never have to do any writebacks). + */ + const bool isReadOnly; + + /** * Bit vector of the blocking reasons for the access path. * @sa #BlockedCause */ @@ -516,6 +524,8 @@ class BaseCache : public MemObject MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) { + // should only see clean evictions in a read-only cache + assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict); assert(pkt->isWrite() && !pkt->isRead()); return allocateBufferInternal(&writeBuffer, blockAlign(pkt->getAddr()), blkSize, diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 117596d9b..5a9205894 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -299,8 +299,13 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, // sanity check assert(pkt->isRequest()); + chatty_assert(!(isReadOnly && pkt->isWrite()), + "Should never see a write in a read-only cache %s\n", + name()); + DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); + if (pkt->req->isUncacheable()) { DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), pkt->req->isInstFetch() ? " (ifetch)" : "", @@ -1419,6 +1424,7 @@ Cache::recvTimingResp(PacketPtr pkt) PacketPtr Cache::writebackBlk(CacheBlk *blk) { + chatty_assert(!isReadOnly, "Writeback from read-only cache"); assert(blk && blk->isValid() && blk->isDirty()); writebacks[Request::wbMasterId]++; @@ -1627,7 +1633,12 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks) blk->status |= BlkValid | BlkReadable; if (!pkt->sharedAsserted()) { + // we could get non-shared responses from memory (rather than + // a cache) even in a read-only cache, note that we set this + // bit even for a read-only cache as we use it to represent + // the exclusive state blk->status |= BlkWritable; + // If we got this via cache-to-cache transfer (i.e., from a // cache that was an owner) and took away that owner's copy, // then we need to write it back. Normally this happens @@ -1635,8 +1646,12 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks) // there are cases (such as failed store conditionals or // compare-and-swaps) where we'll demand an exclusive copy but // end up not writing it. - if (pkt->memInhibitAsserted()) + if (pkt->memInhibitAsserted()) { blk->status |= BlkDirty; + + chatty_assert(!isReadOnly, "Should never see dirty snoop response " + "in read-only cache %s\n", name()); + } } DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", @@ -1785,6 +1800,10 @@ Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, pkt->getAddr(), pkt->getSize(), blk->print()); } + chatty_assert(!(isReadOnly && blk->isDirty()), + "Should never have a dirty block in a read-only cache %s\n", + name()); + // we may end up modifying both the block state and the packet (if // we respond in atomic mode), so just figure out what to do now // and then do it later. If we find dirty data while snooping for a |