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authorBjoern A. Zeeb <baz21@cam.ac.uk>2016-05-19 15:19:35 -0500
committerBjoern A. Zeeb <baz21@cam.ac.uk>2016-05-19 15:19:35 -0500
commita6b00c07f6ec9dd25c860bc89691e3873f7996c6 (patch)
tree5692005b59b3554ded54adeefd500a5bb9f169b9 /src
parent5fa6b68981dd8566bc2808a309f34d40186a74cf (diff)
downloadgem5-a6b00c07f6ec9dd25c860bc89691e3873f7996c6.tar.xz
arm,dev: PL011 UART_FR read status enhancement
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/dev/arm/pl011.cc3
-rw-r--r--src/dev/arm/pl011.hh4
2 files changed, 5 insertions, 2 deletions
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index f0c3d2d98..e00ee8351 100644
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -91,7 +91,8 @@ Pl011::read(PacketPtr pkt)
case UART_FR:
data =
UART_FR_CTS | // Clear To Send
- (!term->dataAvailable() ? UART_FR_RXFE : 0) | // RX FIFO Empty
+ // Given we do not simulate a FIFO we are either empty or full.
+ (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
UART_FR_TXFE; // TX FIFO empty
DPRINTF(Uart,
diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index e19c74fa2..81745eded 100644
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -120,8 +120,10 @@ class Pl011 : public Uart, public AmbaDevice
static const int UART_DR = 0x000;
static const int UART_FR = 0x018;
static const int UART_FR_CTS = 0x001;
- static const int UART_FR_TXFE = 0x080;
static const int UART_FR_RXFE = 0x010;
+ static const int UART_FR_TXFF = 0x020;
+ static const int UART_FR_RXFF = 0x040;
+ static const int UART_FR_TXFE = 0x080;
static const int UART_IBRD = 0x024;
static const int UART_FBRD = 0x028;
static const int UART_LCRH = 0x02C;