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author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
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committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
commit | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (patch) | |
tree | 50a0e9f80288a07de0d60261c529f0c5888e0eb9 /src | |
parent | e4859fae5b5edc6df51f42e2b1859d6c8f7c15f6 (diff) | |
download | gem5-c11bcb8119273ef91c40a25b8fd9471a887d0ee5.tar.xz |
mem: Multi Level Page Table bug fix
The multi level page table was giving false positives for already mapped
translations. This patch fixes the bogus behavior.
Diffstat (limited to 'src')
-rw-r--r-- | src/mem/multi_level_page_table_impl.hh | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh index 063e097c5..3d8cbe75d 100644 --- a/src/mem/multi_level_page_table_impl.hh +++ b/src/mem/multi_level_page_table_impl.hh @@ -151,14 +151,13 @@ MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, if (walk(vaddr, true, PTE_addr)) { PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr); Addr entry_paddr = pTableISAOps.getPnum(PTE); - if (!clobber && entry_paddr == 0) { - pTableISAOps.setPnum(PTE, paddr >> PageShift); - pTableISAOps.setPTEFields(PTE); - p.write<PageTableEntry>(PTE_addr, PTE); - DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr); - } else { + if (!clobber && entry_paddr != 0) { fatal("addr 0x%x already mapped to %x", vaddr, entry_paddr); } + pTableISAOps.setPnum(PTE, paddr >> PageShift); + pTableISAOps.setPTEFields(PTE); + p.write<PageTableEntry>(PTE_addr, PTE); + DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr); eraseCacheEntry(vaddr); updateCache(vaddr, TlbEntry(pid, vaddr, paddr)); |