Ruby: Reorganize mapping of components

In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.

3 files changed, 52 insertions, 90 deletions

diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm
index 3c777e965..4f6f0e3d1 100644
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm
+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm
@@ -30,34 +30,12 @@
 // Mapping functions
 
 int machineCount(MachineType machType);
-
-// NodeID map_address_to_node(Address addr);
 MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
 NetDest broadcast(MachineType type);
 MachineID map_Address_to_DMA(Address addr);
 MachineID map_Address_to_Directory(Address addr);
 NodeID map_Address_to_DirectoryNode(Address addr);
-
-
-MachineID getL1MachineID(NodeID L1RubyNode);
-NodeID getChipID(MachineID L2machID);
-MachineID getCollectorDest(MachineID L1machID);
-MachineID getCollectorL1Cache(MachineID colID);
-NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers);
-bool isL1OnChip(MachineID L1machID, NodeID L2NodeID);
-bool isL2OnChip(MachineID L2machID, NodeID L2NodeID);
-
-int getNumBanksInBankSet();
 NodeID machineIDToNodeID(MachineID machID);
 NodeID machineIDToVersion(MachineID machID);
 MachineType machineIDToMachineType(MachineID machID);
-NodeID L1CacheMachIDToProcessorNum(MachineID machID);
-NodeID L2CacheMachIDToChipID(MachineID machID);
-Set getOtherLocalL1IDs(MachineID L1);
-Set getLocalL1IDs(MachineID L1);
-Set getExternalL1IDs(MachineID L1);
-NetDest getAllPertinentL2Banks(Address addr);
-bool isLocalProcessor(MachineID thisId, MachineID tarId);
-
 GenericMachineType ConvertMachToGenericMach(MachineType machType);
-
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index 18e7ad6fc..14b084c5d 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -29,7 +29,6 @@
 #ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 #define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 
-#include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -38,30 +37,6 @@
 #include "mem/ruby/system/MachineID.hh"
 #include "mem/ruby/system/NodeID.hh"
 
-#ifdef MACHINETYPE_L1Cache
-#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
-#else
-#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM
-#endif
-
-#ifdef MACHINETYPE_L2Cache
-#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache
-#else
-#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM
-#endif
-
-#ifdef MACHINETYPE_L3Cache
-#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache
-#else
-#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM
-#endif
-
-#ifdef MACHINETYPE_DMA
-#define MACHINETYPE_DMA_ENUM MachineType_DMA
-#else
-#define MACHINETYPE_DMA_ENUM MachineType_NUM
-#endif
-
 // used to determine the home directory
 // returns a value between 0 and total_directories_within_the_system
 inline NodeID
@@ -80,13 +55,6 @@ map_Address_to_Directory(const Address &addr)
     return mach;
 }
 
-inline MachineID
-map_Address_to_DMA(const Address & addr)
-{
-    MachineID dma = {MACHINETYPE_DMA_ENUM, 0};
-    return dma;
-}
-
 inline NetDest
 broadcast(MachineType type)
 {
@@ -121,41 +89,6 @@ machineIDToMachineType(MachineID machID)
     return machID.type;
 }
 
-inline NodeID
-L1CacheMachIDToProcessorNum(MachineID machID)
-{
-    assert(machID.type == MACHINETYPE_L1CACHE_ENUM);
-    return machID.num;
-}
-
-inline MachineID
-getL1MachineID(NodeID L1RubyNode)
-{
-    MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode};
-    return mach;
-}
-
-inline GenericMachineType
-ConvertMachToGenericMach(MachineType machType)
-{
-    if (machType == MACHINETYPE_L1CACHE_ENUM)
-        return GenericMachineType_L1Cache;
-
-    if (machType == MACHINETYPE_L2CACHE_ENUM)
-        return GenericMachineType_L2Cache;
-
-    if (machType == MACHINETYPE_L3CACHE_ENUM)
-        return GenericMachineType_L3Cache;
-
-    if (machType == MachineType_Directory)
-        return GenericMachineType_Directory;
-
-    if (machType == MACHINETYPE_DMA_ENUM)
-        return GenericMachineType_DMA;
-
-    panic("cannot convert to a GenericMachineType");
-}
-
 inline int
 machineCount(MachineType machType)
 {
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index b41ecc00f..36be8c25a 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -444,6 +444,13 @@ ${{self.c_ident}}::print(ostream& out) const
         if self.isStateDecl:
             code('#include "mem/protocol/AccessPermission.hh"')
 
+        if self.isMachineType:
+            code('#include "base/misc.hh"')
+            code('#include "mem/protocol/GenericMachineType.hh"')
+            code('#include "mem/ruby/common/Address.hh"')
+            code('#include "mem/ruby/system/NodeID.hh"')
+            code('struct MachineID;')
+
         code('''
 
 // Class definition
@@ -488,7 +495,29 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj);
 ''')
 
             for enum in self.enums.itervalues():
-                code('#define MACHINETYPE_${{enum.ident}} 1')
+                if enum.ident == "DMA":
+                    code('''
+MachineID map_Address_to_DMA(const Address &addr);
+''')
+                code('''
+
+MachineID get${{enum.ident}}MachineID(NodeID RubyNode);
+''')
+
+            code('''
+inline GenericMachineType
+ConvertMachToGenericMach(MachineType machType)
+{
+''')
+            for enum in self.enums.itervalues():
+                code('''
+      if (machType == MachineType_${{enum.ident}})
+          return GenericMachineType_${{enum.ident}};
+''')
+            code('''
+      panic("cannot convert to a GenericMachineType");
+}
+''')
 
         if self.isStateDecl:
             code('''
@@ -550,6 +579,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
         if self.isMachineType:
             for enum in self.enums.itervalues():
                 code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
+            code('#include "mem/ruby/system/MachineID.hh"')
 
         code('''
 // Code for output operator
@@ -723,6 +753,27 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
 }
 ''')
 
+            for enum in self.enums.itervalues():
+                if enum.ident == "DMA":
+                    code('''
+MachineID
+map_Address_to_DMA(const Address &addr)
+{
+      MachineID dma = {MachineType_DMA, 0};
+      return dma;
+}
+''')
+
+                code('''
+
+MachineID
+get${{enum.ident}}MachineID(NodeID RubyNode)
+{
+      MachineID mach = {MachineType_${{enum.ident}}, RubyNode};
+      return mach;
+}
+''')
+
         # Write the file
         code.write(path, "%s.cc" % self.c_ident)