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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-13 18:01:23 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-13 18:01:23 +0000 |
| commit | dc13db857861ed1a52d84790d64ab6af233f4833 (patch) | |
| tree | e712306f28bb99e27701cd4ab6c8892814184c22 /src | |
| parent | 4e7786d971dc0a0418c08aa595447c04facd93d5 (diff) | |
| download | gem5-dc13db857861ed1a52d84790d64ab6af233f4833.tar.xz | |
Fix the immediate version of register operations, and get their name to show up correctly.
--HG--
extra : convert_revision : 9fc36b99c9027e35f22983d5d1e22c940fa093de
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index c2aa27b67..a99194c5e 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -231,11 +231,10 @@ let {{ self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + allocator = '''new %(class_name)s(machInst, mnemonic %(flags)s, %(src1)s, %(src2)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, - "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "src2" : self.src2, "dest" : self.dest, @@ -245,20 +244,19 @@ let {{ return allocator class RegOpImm(X86Microop): - def __init__(self, dest, src1, imm): + def __init__(self, dest, src1, imm8): self.dest = dest self.src1 = src1 - self.imm = imm + self.imm8 = imm8 self.setStatus = False self.dataSize = 1 self.ext = 0 def getAllocator(self, *microFlags): - allocator = '''new %(class_name)s(machInst, "%(mnemonic)s" + allocator = '''new %(class_name)s(machInst, mnemonic %(flags)s, %(src1)s, %(imm8)s, %(dest)s, %(setStatus)s, %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, - "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "imm8" : self.imm8, "dest" : self.dest, @@ -318,7 +316,7 @@ let {{ self.className = Name + "Imm" self.mnemonic = name + "i" - microopClasses[name + "i"] = RegOpChild + microopClasses[name + "i"] = RegOpImmChild defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') |