config: Do not use hardcoded physmem in fs script

This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.

The change is needed to allow interleaved memory controllers in the
system.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/sim/System.py b/src/sim/System.py
index 3d45c23c0..69ae61e8f 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -62,6 +62,12 @@ class System(MemObject):
     memories = VectorParam.AbstractMemory(Self.all,
                                           "All memories in the system")
     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
+
+    # The memory ranges are to be populated when creating the system
+    # such that these can be passed from the I/O subsystem through an
+    # I/O bridge or cache
+    mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
+
     work_item_id = Param.Int(-1, "specific work item id")
     num_work_ids = Param.Int(16, "Number of distinct work item types")
     work_begin_cpu_id_exit = Param.Int(-1,