cpu: Remove all notion that we know when the cpu is misspeculating.

We have no way of knowing if a CPU model is on the wrong path with
our execute-in-execute CPU models. Don't pretend that we do.

16 files changed, 21 insertions, 86 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index d66ab42aa..d45786a83 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -161,8 +161,7 @@ ISA::readIpr(int idx, ThreadContext *tc)
 
       case IPR_DTB_PTE:
         {
-            TlbEntry &entry
-                = tc->getDTBPtr()->index(!tc->misspeculating());
+            TlbEntry &entry = tc->getDTBPtr()->index(1);
 
             retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
@@ -202,9 +201,6 @@ int break_ipl = -1;
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
-    if (tc->misspeculating())
-        return;
-
     switch (idx) {
       case IPR_PALtemp0:
       case IPR_PALtemp1:
@@ -484,10 +480,8 @@ SimpleThread::hwrei()
 
     CPA::cpa()->swAutoBegin(tc, pc.npc());
 
-    if (!misspeculating()) {
-        if (kernelStats)
-            kernelStats->hwrei();
-    }
+    if (kernelStats)
+        kernelStats->hwrei();
 
     // FIXME: XXX check for interrupts? XXX
     return NoFault;
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 6375b0bfb..2928f8d65 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -147,8 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         // on VPTE loads (instead of locking the registers until IPR_VA is
         // read, like the EV5).  The EV6 approach is cleaner and seems to
         // work with EV5 PAL code, but not the other way around.
-        if (!tc->misspeculating() &&
-            reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+        if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
             // set VA register with faulting address
             tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
@@ -172,11 +171,9 @@ void
 ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     if (FullSystem) {
-        if (!tc->misspeculating()) {
-            tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
-            tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-                tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
-        }
+        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 88ea535b7..22388e6d9 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -81,7 +81,6 @@ DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
 DebugFlag('ExecOpClass', 'Format: Include operand class')
 DebugFlag('ExecRegDelta')
 DebugFlag('ExecResult', 'Format: Include results from execution')
-DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
 DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
 DebugFlag('ExecThread', 'Format: Include thread ID in trace')
 DebugFlag('ExecTicks', 'Format: Include tick count')
@@ -100,7 +99,7 @@ DebugFlag('Mwait')
 
 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
-    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+    'ExecResult', 'ExecSymbol', 'ExecThread',
     'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
     'ExecAsid', 'ExecFlags' ])
 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 590cef004..ccf0d3c1d 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -310,9 +310,6 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setStCondFailures(sc_failures);
     }
 
-    // @todo: Fix this!
-    bool misspeculating() { return actualTC->misspeculating(); }
-
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 
     uint64_t readIntRegFlat(int idx)
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 9e08dca00..345adbc81 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -71,9 +71,6 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
 
     outs << thread->getCpuPtr()->name() << " ";
 
-    if (Debug::ExecSpeculative)
-        outs << (misspeculating ? "-" : "+") << " ";
-
     if (Debug::ExecAsid)
         outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
 
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index ebb712af6..51a8c05c9 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -37,7 +37,6 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "debug/ExecEnable.hh"
-#include "debug/ExecSpeculative.hh"
 #include "params/ExeTracer.hh"
 #include "sim/insttracer.hh"
 
@@ -50,9 +49,8 @@ class ExeTracerRecord : public InstRecord
   public:
     ExeTracerRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst, TheISA::PCState _pc,
-               bool spec, const StaticInstPtr _macroStaticInst = NULL)
-        : InstRecord(_when, _thread, _staticInst, _pc, spec,
-                _macroStaticInst)
+               const StaticInstPtr _macroStaticInst = NULL)
+        : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
     {
     }
 
@@ -80,11 +78,8 @@ class ExeTracer : public InstTracer
         if (!Trace::enabled)
             return NULL;
 
-        if (!Debug::ExecSpeculative && tc->misspeculating())
-            return NULL;
-
         return new ExeTracerRecord(when, tc,
-                staticInst, pc, tc->misspeculating(), macroStaticInst);
+                staticInst, pc, macroStaticInst);
     }
 };
 
diff --git a/src/cpu/inorder/inorder_trace.hh b/src/cpu/inorder/inorder_trace.hh
index 5386f641d..bb90f305e 100644
--- a/src/cpu/inorder/inorder_trace.hh
+++ b/src/cpu/inorder/inorder_trace.hh
@@ -47,8 +47,8 @@ class InOrderTraceRecord : public ExeTracerRecord
 {
   public:
     InOrderTraceRecord(unsigned num_stages, bool _stage_tracing,
-           ThreadContext *_thread, TheISA::PCState _pc, bool spec = false)
-        : ExeTracerRecord(0, _thread, NULL, _pc, spec)
+           ThreadContext *_thread, TheISA::PCState _pc)
+        : ExeTracerRecord(0, _thread, NULL, _pc)
     {
         stageTrace = _stage_tracing;
         stageCycle.resize(num_stages);
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 7b1dc833f..022beaaee 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -290,14 +290,6 @@ class InOrderThreadContext : public ThreadContext
     void setStCondFailures(unsigned sc_failures)
     { thread->storeCondFailures = sc_failures; }
 
-    // Only really makes sense for old CPU model.  Lots of code
-    // outside the CPU still checks this function, so it will
-    // always return false to keep everything working.
-    /** Checks if the thread is misspeculating.  Because it is
-     * very difficult to determine if the thread is
-     * misspeculating, this is set as false. */
-    bool misspeculating() { return false; }
-
     /** Executes a syscall in SE mode. */
     void syscall(int64_t callnum)
     { return cpu->syscall(callnum, thread->threadId()); }
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index e5f88bf1a..4ddf5eac9 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -37,7 +37,6 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "debug/ExecEnable.hh"
-#include "debug/ExecSpeculative.hh"
 #include "params/IntelTrace.hh"
 #include "sim/insttracer.hh"
 
@@ -48,8 +47,8 @@ class IntelTraceRecord : public InstRecord
   public:
     IntelTraceRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst, TheISA::PCState _pc,
-               bool spec, const StaticInstPtr _macroStaticInst = NULL)
-        : InstRecord(_when, _thread, _staticInst, _pc, spec,
+               const StaticInstPtr _macroStaticInst = NULL)
+        : InstRecord(_when, _thread, _staticInst, _pc,
                 _macroStaticInst)
     {
     }
@@ -75,11 +74,7 @@ class IntelTrace : public InstTracer
         if (!Trace::enabled)
             return NULL;
 
-        if (!Debug::ExecSpeculative && tc->misspeculating())
-            return NULL;
-
-        return new IntelTraceRecord(when, tc,
-                staticInst, pc, tc->misspeculating(), macroStaticInst);
+        return new IntelTraceRecord(when, tc, staticInst, pc, macroStaticInst);
     }
 };
 
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index f6bf63d76..d91dbd6ec 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -56,9 +56,8 @@ class NativeTraceRecord : public ExeTracerRecord
     NativeTraceRecord(NativeTrace * _parent,
                Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst, TheISA::PCState _pc,
-               bool spec, const StaticInstPtr _macroStaticInst = NULL)
-        : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec,
-                _macroStaticInst),
+               const StaticInstPtr _macroStaticInst = NULL)
+        : ExeTracerRecord(_when, _thread, _staticInst, _pc, _macroStaticInst),
         parent(_parent)
     {
     }
@@ -83,11 +82,8 @@ class NativeTrace : public ExeTracer
             const StaticInstPtr staticInst, TheISA::PCState pc,
             const StaticInstPtr macroStaticInst = NULL)
     {
-        if (tc->misspeculating())
-            return NULL;
-
         return new NativeTraceRecord(this, when, tc,
-                staticInst, pc, tc->misspeculating(), macroStaticInst);
+                staticInst, pc, macroStaticInst);
     }
 
     template<class T>
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b27fbb386..952d365bf 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -257,14 +257,6 @@ class O3ThreadContext : public ThreadContext
     virtual void setStCondFailures(unsigned sc_failures)
     { thread->storeCondFailures = sc_failures; }
 
-    // Only really makes sense for old CPU model.  Lots of code
-    // outside the CPU still checks this function, so it will
-    // always return false to keep everything working.
-    /** Checks if the thread is misspeculating.  Because it is
-     * very difficult to determine if the thread is
-     * misspeculating, this is set as false. */
-    virtual bool misspeculating() { return false; }
-
     /** Executes a syscall in SE mode. */
     virtual void syscall(int64_t callnum)
     { return cpu->syscall(callnum, thread->threadId()); }
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 45dfaf4b4..7ace2204a 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -449,7 +449,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
         thread->syscall(callnum);
     }
 
-    bool misspeculating() { return thread->misspeculating(); }
     ThreadContext *tcBase() { return tc; }
 
   private:
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6b8f3063a..1f9e58ad9 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -220,8 +220,6 @@ class SimpleThread : public ThreadState
     /// Set the status to Halted.
     void halt();
 
-    virtual bool misspeculating();
-
     void copyArchRegs(ThreadContext *tc);
 
     void clearArchRegs()
@@ -455,11 +453,4 @@ class SimpleThread : public ThreadState
 };
 
 
-// for non-speculative execution context, spec_mode is always false
-inline bool
-SimpleThread::misspeculating()
-{
-    return false;
-}
-
 #endif // __CPU_CPU_EXEC_CONTEXT_HH__
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 95d89dcc5..850ff9468 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -255,9 +255,6 @@ class ThreadContext
 
     virtual void setStCondFailures(unsigned sc_failures) = 0;
 
-    // Only really makes sense for old CPU model.  Still could be useful though.
-    virtual bool misspeculating() = 0;
-
     // Same with st cond failures.
     virtual Counter readFuncExeInst() = 0;
 
@@ -462,9 +459,6 @@ class ProxyThreadContext : public ThreadContext
     void setStCondFailures(unsigned sc_failures)
     { actualTC->setStCondFailures(sc_failures); }
 
-    // @todo: Fix this!
-    bool misspeculating() { return actualTC->misspeculating(); }
-
     void syscall(int64_t callnum)
     { actualTC->syscall(callnum); }
 
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index e2562fca6..abcad6d3c 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -43,7 +43,6 @@ void FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
 {
     if (FullSystem) {
         DPRINTF(Fault, "Fault %s at PC: %s\n", name(), tc->pcState());
-        assert(!tc->misspeculating());
     } else {
         panic("fault (%s) detected @ PC %s", name(), tc->pcState());
     }
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index df1f12766..b4605a2c9 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -56,7 +56,6 @@ class InstRecord
     StaticInstPtr staticInst;
     TheISA::PCState pc;
     StaticInstPtr macroStaticInst;
-    bool misspeculating;
     bool predicate;
 
     // The remaining fields are only valid for particular instruction
@@ -89,12 +88,12 @@ class InstRecord
   public:
     InstRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst,
-               TheISA::PCState _pc, bool spec,
+               TheISA::PCState _pc,
                const StaticInstPtr _macroStaticInst = NULL)
         : when(_when), thread(_thread),
           staticInst(_staticInst), pc(_pc),
           macroStaticInst(_macroStaticInst),
-          misspeculating(spec), predicate(true), addr(0), addr_valid(false),
+          predicate(true), addr(0), addr_valid(false),
           data_status(DataInvalid),
           fetch_seq(0), fetch_seq_valid(false), cp_seq(0), cp_seq_valid(false)
     {
@@ -136,7 +135,6 @@ class InstRecord
     StaticInstPtr getStaticInst() { return staticInst; }
     TheISA::PCState getPCState() { return pc; }
     StaticInstPtr getMacroStaticInst() { return macroStaticInst; }
-    bool getMisspeculating() { return misspeculating; }
 
     Addr getAddr() { return addr; }
     bool getAddrValid() { return addr_valid; }