slicc: improved stalling support in protocols

Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions.  Also insures that resource and
protocol stalls are re-evaluated the next cycle.

5 files changed, 56 insertions, 1 deletions

diff --git a/src/mem/slicc/ast/CheckNextCycleAST.py b/src/mem/slicc/ast/CheckNextCycleAST.py
new file mode 100644
index 000000000..5ca869d57
--- /dev/null
+++ b/src/mem/slicc/ast/CheckNextCycleAST.py
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2013-15 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from slicc.ast.StatementAST import StatementAST
+
+class CheckNextCycleAST(StatementAST):
+    def __init__(self, slicc):
+        super(CheckNextCycleAST, self).__init__(slicc)
+
+    def __repr__(self):
+        return "[CheckNextCycleAST]"
+
+    def generate(self, code, return_type):
+        code("scheduleEvent(Cycles(1));")
+        return "CheckNextCycle"
diff --git a/src/mem/slicc/ast/FuncCallExprAST.py b/src/mem/slicc/ast/FuncCallExprAST.py
index ad95bc884..8aebad336 100644
--- a/src/mem/slicc/ast/FuncCallExprAST.py
+++ b/src/mem/slicc/ast/FuncCallExprAST.py
@@ -145,7 +145,8 @@ class FuncCallExprAST(ExprAST):
         continue; // Check the first port again
     }
 
-    if (result == TransitionResult_ResourceStall) {
+    if (result == TransitionResult_ResourceStall ||
+        result == TransitionResult_ProtocolStall) {
         scheduleEvent(Cycles(1));
 
         // Cannot do anything with this transition, go check next doable transition (mostly likely of next port)
@@ -172,6 +173,8 @@ if (!(${{cvec[0]}})) {
             code("set_tbe(m_tbe_ptr, %s);" %(cvec[0]));
         elif self.proc_name == "unset_tbe":
             code("unset_tbe(m_tbe_ptr);");
+        elif self.proc_name == "stallPort":
+            code("scheduleEvent(Cycles(1));")
 
         else:
             # Normal function
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index c5539fe52..c5a1435eb 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -89,6 +89,12 @@ class InPortDeclAST(DeclAST):
                     param_types, [], "", pairs)
         symtab.newSymbol(func)
 
+        # Add the stallPort method - this hacks reschedules the controller
+        # for stalled messages that don't trigger events
+        func = Func(self.symtab, "stallPort", self.location, void_type, [],
+                    [], "", pairs)
+        symtab.newSymbol(func)
+
         param_types = []
         # Check for Event2
         type = symtab.find("Event", Type)
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index 9fc52eff8..c5c616a55 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -30,6 +30,7 @@ from slicc.ast.AST import *
 from slicc.ast.ActionDeclAST import *
 from slicc.ast.AssignStatementAST import *
 from slicc.ast.CheckAllocateStatementAST import *
+from slicc.ast.CheckNextCycleAST import *
 from slicc.ast.DeclAST import *
 from slicc.ast.DeclListAST import *
 from slicc.ast.EnqueueStatementAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 1ce8bf1bd..0cbe9ea63 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -113,6 +113,7 @@ class SLICC(Grammar):
         'stall_and_wait' : 'STALL_AND_WAIT',
         'enqueue' : 'ENQUEUE',
         'check_allocate' : 'CHECK_ALLOCATE',
+        'check_next_cycle' : 'CHECK_NEXT_CYCLE',
         'check_stop_slots' : 'CHECK_STOP_SLOTS',
         'static_cast' : 'STATIC_CAST',
         'if' : 'IF',
@@ -597,6 +598,10 @@ class SLICC(Grammar):
         "statement : CHECK_ALLOCATE '(' var ')' SEMI"
         p[0] = ast.CheckAllocateStatementAST(self, p[3])
 
+    def p_statement__check_next_cycle(self, p):
+        "statement : CHECK_NEXT_CYCLE '(' ')' SEMI"
+        p[0] = ast.CheckNextCycleAST(self)
+
     def p_statement__check_stop(self, p):
         "statement : CHECK_STOP_SLOTS '(' var ',' STRING ',' STRING ')' SEMI"
         p[0] = ast.CheckStopStatementAST(self, p[3], p[5], p[7])