diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-11-14 17:22:32 -0500 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-11-14 17:22:32 -0500 |
commit | 069c7c30d1c871aba937a6a4ee7b1146d716ac4b (patch) | |
tree | 1d2c04c1c1beff2c9238cc87dc52016d8f7aeac3 /src | |
parent | 2f6a9454d13e44faba55b14d958f20a04bc36246 (diff) | |
download | gem5-069c7c30d1c871aba937a6a4ee7b1146d716ac4b.tar.xz |
Various fixes to delete packet and request a little better.
src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
--HG--
extra : convert_revision : c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/simple/timing.cc | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index db2c940c0..d75688ee6 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -281,6 +281,8 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) // memory system takes ownership of packet dcache_pkt = NULL; } + } else { + delete req; } // This will need a new way to tell if it has a dcache attached. @@ -366,6 +368,8 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_pkt = NULL; } } + } else { + delete req; } // This will need a new way to tell if it's hooked up to a cache or not. @@ -448,6 +452,8 @@ TimingSimpleCPU::fetch() ifetch_pkt = NULL; } } else { + delete ifetch_req; + delete ifetch_pkt; // fetch fault: advance directly to next instruction (fault handler) advanceInst(fault); } @@ -481,13 +487,13 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = Running; - delete pkt->req; - delete pkt; - numCycles += curTick - previousTick; previousTick = curTick; if (getState() == SimObject::Draining) { + delete pkt->req; + delete pkt; + completeDrain(); return; } @@ -519,6 +525,9 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) postExecute(); advanceInst(fault); } + + delete pkt->req; + delete pkt; } void |