diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-30 17:13:54 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-14 13:45:07 +0000 |
| commit | 831184d2949fbd790a2040738079ca03c8cfdefe (patch) | |
| tree | 3432bff52f11da340cf04bdf3196a11c11c9fda6 /src | |
| parent | 4a37134f5f739a2cfed6426d296f7755044d2d28 (diff) | |
| download | gem5-831184d2949fbd790a2040738079ca03c8cfdefe.tar.xz | |
arch-arm: Read APSR in User Mode
This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.
Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index f1c6acff3..ef579bf5a 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -226,7 +226,7 @@ let {{ cpsr.c = CondCodesC; cpsr.v = CondCodesV; cpsr.ge = CondCodesGE; - Dest = cpsr & 0xF8FF03DF + Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask); ''' mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index b00e5ff66..f9386b412 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1423,6 +1423,17 @@ namespace ArmISA static const uint32_t CondCodesMask = 0xF00F0000; static const uint32_t CpsrMaskQ = 0x08000000; + // APSR (Application Program Status Register Mask). It is the user level + // alias for the CPSR. The APSR is a subset of the CPSR. Although + // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of + // APSR: + // Bit[9] returns the value of CPSR.E. + // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits. + static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0; + + // CPSR (Current Program Status Register Mask). + static const uint32_t CpsrMask = ApsrMask | 0x00F003DF; + BitUnion32(HDCR) Bitfield<11> tdra; Bitfield<10> tdosa; |