diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:27 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:27 -0500 |
commit | afd08879d726dbbefa3ff6018088cd6d89b53bbb (patch) | |
tree | f77a8147770c772ce05933f9b96a615049a70263 /src | |
parent | f7380052669eb7030e73d4799fb448ffc8e78680 (diff) | |
download | gem5-afd08879d726dbbefa3ff6018088cd6d89b53bbb.tar.xz |
ARM: Add support for some more registers in the real view controller.
Diffstat (limited to 'src')
-rw-r--r-- | src/dev/arm/rv_ctrl.cc | 10 | ||||
-rw-r--r-- | src/dev/arm/rv_ctrl.hh | 7 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc index f9cdbe8a1..e24fea737 100644 --- a/src/dev/arm/rv_ctrl.cc +++ b/src/dev/arm/rv_ctrl.cc @@ -43,7 +43,7 @@ #include "mem/packet_access.hh" RealViewCtrl::RealViewCtrl(Params *p) - : BasicPioDevice(p) + : BasicPioDevice(p), flags(0) { pioSize = 0xD4; } @@ -94,6 +94,9 @@ RealViewCtrl::read(PacketPtr pkt) case Lock: pkt->set<uint32_t>(sysLock); break; + case Flags: + pkt->set<uint32_t>(flags); + break; default: panic("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr); break; @@ -121,6 +124,9 @@ RealViewCtrl::write(PacketPtr pkt) case Lock: sysLock.lockVal = pkt->get<uint16_t>(); break; + case Flags: + flags = pkt->get<uint32_t>(); + break; default: panic("Tried to write RVIO at offset %#x that doesn't exist\n", daddr); break; @@ -132,11 +138,13 @@ RealViewCtrl::write(PacketPtr pkt) void RealViewCtrl::serialize(std::ostream &os) { + SERIALIZE_SCALAR(flags); } void RealViewCtrl::unserialize(Checkpoint *cp, const std::string §ion) { + UNSERIALIZE_SCALAR(flags); } RealViewCtrl * diff --git a/src/dev/arm/rv_ctrl.hh b/src/dev/arm/rv_ctrl.hh index ceed5ef2f..255b21c0f 100644 --- a/src/dev/arm/rv_ctrl.hh +++ b/src/dev/arm/rv_ctrl.hh @@ -95,6 +95,13 @@ class RealViewCtrl : public BasicPioDevice SysLockReg sysLock; + /** This register is used for smp booting. + * The primary cpu writes the secondary start address here before + * sends it a soft interrupt. The secondary cpu reads this register and if + * it's non-zero it jumps to the address + */ + uint32_t flags; + public: typedef RealViewCtrlParams Params; const Params * |