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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
commit2e4ddbd234068efd392e0523e9d3a6eb21a210f0 (patch)
tree1f2fae8c67b61cfcda45578850d1f4a08f6e7d50 /src
parent6106bd18cd74fd20bc3d4da8fe3884c4401e067f (diff)
downloadgem5-2e4ddbd234068efd392e0523e9d3a6eb21a210f0.tar.xz
ARM: Decode the VSTR instruction.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/formats/fp.isa39
1 files changed, 30 insertions, 9 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index b3032b6fb..77d6d8e9e 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -219,23 +219,40 @@ def format ExtensionRegLoadStore() {{
}
// Fall through on purpose
case 0x3:
+ const bool up = (bits(machInst, 23) == 1);
+ const uint32_t imm = bits(machInst, 7, 0) << 2;
+ RegIndex vd;
+ if (single) {
+ vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
+ (bits(machInst, 22)));
+ } else {
+ vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
+ (bits(machInst, 22) << 5));
+ }
if (bits(opcode, 1, 0) == 0x0) {
- return new WarnUnimplemented("vstr", machInst);
+ if (single) {
+ if (up) {
+ return new %(vstr_us)s(machInst, vd, rn, up, imm);
+ } else {
+ return new %(vstr_s)s(machInst, vd, rn, up, imm);
+ }
+ } else {
+ if (up) {
+ return new %(vstr_ud)s(machInst, vd, vd + 1,
+ rn, up, imm);
+ } else {
+ return new %(vstr_d)s(machInst, vd, vd + 1,
+ rn, up, imm);
+ }
+ }
} else if (bits(opcode, 1, 0) == 0x1) {
- const bool up = (bits(machInst, 23) == 1);
- const uint32_t imm = bits(machInst, 7, 0) << 2;
- RegIndex vd;
if (single) {
- vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
- (bits(machInst, 22)));
if (up) {
return new %(vldr_us)s(machInst, vd, rn, up, imm);
} else {
return new %(vldr_s)s(machInst, vd, rn, up, imm);
}
} else {
- vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
- (bits(machInst, 22) << 5));
if (up) {
return new %(vldr_ud)s(machInst, vd, vd + 1,
rn, up, imm);
@@ -252,7 +269,11 @@ def format ExtensionRegLoadStore() {{
"vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
"vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
"vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
- "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False)
+ "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
+ "vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
+ "vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
+ "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
+ "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
}
}};