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authorAli Saidi <Ali.Saidi@ARM.com>2012-05-10 18:04:27 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-05-10 18:04:27 -0500
commit5ecaf30219d8a846f2747d4d67503c21c6e13333 (patch)
tree44a04405c74c9c3441f2a775cf3360cc46f5e8f3 /src
parentda10fbf5ca53313e20b19457fad780bd6c8930b2 (diff)
downloadgem5-5ecaf30219d8a846f2747d4d67503c21c6e13333.tar.xz
gem5: fix a number of use after free issues
Diffstat (limited to 'src')
-rw-r--r--src/cpu/checker/cpu.cc3
-rw-r--r--src/sim/eventq.hh6
2 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 901c3900f..73205dc35 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -264,13 +264,14 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
* enabled. This is left as future work for the Checker: LSQ snooping
* and memory validation after stores have committed.
*/
+ bool was_prefetch = memReq->isPrefetch();
delete memReq;
//If we don't need to access a second cache line, stop now.
if (fault != NoFault || secondAddr <= addr)
{
- if (fault != NoFault && memReq->isPrefetch()) {
+ if (fault != NoFault && was_prefetch) {
fault = NoFault;
}
break;
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index c859823c8..e7d088e80 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -516,11 +516,11 @@ EventQueue::deschedule(Event *event)
event->flags.clear(Event::Squashed);
event->flags.clear(Event::Scheduled);
- if (event->flags.isSet(Event::AutoDelete))
- delete event;
-
if (DTRACE(Event))
event->trace("descheduled");
+
+ if (event->flags.isSet(Event::AutoDelete))
+ delete event;
}
inline void