summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
commit65a5177b53c53b287125cec3f207afeec648d488 (patch)
tree0f513ad6bc197f02676c368520629f863a202d82 /src
parent2e4ddbd234068efd392e0523e9d3a6eb21a210f0 (diff)
downloadgem5-65a5177b53c53b287125cec3f207afeec648d488.tar.xz
ARM: Undef instruction on invalid user CP15 access
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/insts/misc.isa26
1 files changed, 24 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 2e3fb2031..6cd4437d0 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -501,15 +501,37 @@ let {{
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
exec_output += PredOpExecute.subst(bfiIop)
+ mrc15code = '''
+ CPSR cpsr = Cpsr;
+ if (cpsr.mode == MODE_USER)
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(false, mnemonic);
+#endif
+ Dest = MiscOp1;
+ '''
+
mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
- { "code": "Dest = MiscOp1;",
+ { "code": mrc15code,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mrc15Iop)
decoder_output += RegRegOpConstructor.subst(mrc15Iop)
exec_output += PredOpExecute.subst(mrc15Iop)
+
+ mcr15code = '''
+ CPSR cpsr = Cpsr;
+ if (cpsr.mode == MODE_USER)
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(false, mnemonic);
+#endif
+ MiscDest = Op1;
+ '''
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
- { "code": "MiscDest = Op1;",
+ { "code": mcr15code,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mcr15Iop)
decoder_output += RegRegOpConstructor.subst(mcr15Iop)