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authorSteve Reinhardt <stever@eecs.umich.edu>2007-06-29 13:03:36 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-06-29 13:03:36 -0700
commit749126e01183821a4c22f27deb0906aa01033206 (patch)
tree214a1ebd0ad62b01a5d808298471869b2e6d61ff /src
parent7f3dfa7c09e0b708e1c873997f191d640751541d (diff)
parent738ecc495b7f296c1344285337601e3d0ad52e71 (diff)
downloadgem5-749126e01183821a4c22f27deb0906aa01033206.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 1e94283da8007fce8e1a0f2849ce5d5a8dbbaffd
Diffstat (limited to 'src')
-rw-r--r--src/arch/mips/isa/decoder.isa21
-rw-r--r--src/arch/mips/isa/formats/fp.isa4
-rw-r--r--src/arch/mips/isa/formats/mem.isa6
3 files changed, 12 insertions, 19 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 0af84e36b..e55d2e070 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -27,6 +27,7 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell
+// Brett Miller
////////////////////////////////////////////////////////////////////
//
@@ -557,20 +558,12 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x1F: deret({{
- // if(EJTagImplemented()) {
- if(Debug_DM == 1){
- Debug_DM = 1;
- Debug_IEXI = 0;
- NPC = DEPC;
- }
- else
- {
- // Undefined;
- }
- //} // EJTag Implemented
- //else {
- // Reserved Instruction Exception
- //}
+ //if(Debug_DM == 1){
+ //Debug_DM = 1;
+ //Debug_IEXI = 0;
+ //NPC = DEPC;
+ //}
+ panic("deret not implemented");
}});
}
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 4b340e2e6..4e81ae2cf 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -150,8 +150,10 @@ output exec {{
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
+ uint32_t new_fcsr = genInvalidVector(fcsr_bits);
+
//Write FCSR from FloatRegFile
- cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits));
+ cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
if (traceData) { traceData->setData(mips_nan); }
return true;
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 81e231810..18d1f52f9 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -369,7 +369,6 @@ def template StoreMemAccExecute {{
{
Addr EA;
Fault fault = NoFault;
- uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
@@ -383,7 +382,7 @@ def template StoreMemAccExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
+ memAccessFlags, NULL);
// @NOTE: Need to Call Complete Access to Set Trace Data
//if (traceData) { traceData->setData(Mem); }
}
@@ -434,7 +433,6 @@ def template StoreExecute {{
{
Addr EA;
Fault fault = NoFault;
- uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
@@ -447,7 +445,7 @@ def template StoreExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
+ memAccessFlags, NULL);
if (traceData) { traceData->setData(Mem); }
}