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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-01-03 14:35:43 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-01-03 14:35:43 -0800 |
| commit | c69d48f007d2521fdbea52a0a7a95cfc4a547174 (patch) | |
| tree | 59a866d2f48310090b5dd18dad0095029314cb6f /src | |
| parent | 1a10ccc5e551857fc3a7c049df99547ccfe3f72b (diff) | |
| download | gem5-c69d48f007d2521fdbea52a0a7a95cfc4a547174.tar.xz | |
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
Diffstat (limited to 'src')
112 files changed, 127 insertions, 127 deletions
diff --git a/src/SConscript b/src/SConscript index 2d4ad7b0c..7d342e04c 100644 --- a/src/SConscript +++ b/src/SConscript @@ -835,7 +835,7 @@ extern const int numFlagStrings; // base flags to set. Inidividual flag arrays are terminated by -1. extern const Flags *compoundFlags[]; -/* namespace Trace */ } +} // namespace Trace #endif // __BASE_TRACE_FLAGS_HH__ ''') @@ -902,7 +902,7 @@ EmbeddedPython embedded_${sym}( ${{len(data)}}, ${{len(marshalled)}}); -/* namespace */ } +} // anonymous namespace ''') code.write(str(target[0])) diff --git a/src/arch/alpha/mt.hh b/src/arch/alpha/mt.hh index 88ab01e32..57cf90f79 100644 --- a/src/arch/alpha/mt.hh +++ b/src/arch/alpha/mt.hh @@ -66,6 +66,6 @@ getTargetThread(TC *tc) return 0; } -}//namespace AlphaISA +} // namespace AlphaISA #endif diff --git a/src/arch/alpha/pagetable.cc b/src/arch/alpha/pagetable.cc index 6640e72e2..4dff04777 100644 --- a/src/arch/alpha/pagetable.cc +++ b/src/arch/alpha/pagetable.cc @@ -61,4 +61,4 @@ TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(valid); } -} //namespace AlphaISA +} // namespace AlphaISA diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 614061ddd..58d54e790 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -595,7 +595,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, translation->finish(translateAtomic(req, tc, mode), req, tc, mode); } -/* end namespace AlphaISA */ } +} // namespace AlphaISA AlphaISA::TLB * AlphaTLBParams::create() diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index a68e7b2ef..6c1b223ab 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -246,6 +246,6 @@ static inline Fault genMachineCheckFault() return new Reset(); } -} // ArmISA namespace +} // namespace ArmISA #endif // __ARM_FAULTS_HH__ diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index a24852ba9..b2989e4b3 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -48,7 +48,7 @@ #include "arch/arm/types.hh" #include "base/types.hh" -namespace LittleEndianGuest {}; +namespace LittleEndianGuest {} #define TARGET_ARM @@ -123,7 +123,7 @@ namespace ArmISA INT_FIQ, NumInterruptTypes }; -}; +} // namespace ArmISA using namespace ArmISA; diff --git a/src/arch/arm/kernel_stats.hh b/src/arch/arm/kernel_stats.hh index 18bdc500d..be5c25bd5 100644 --- a/src/arch/arm/kernel_stats.hh +++ b/src/arch/arm/kernel_stats.hh @@ -51,7 +51,7 @@ class Statistics : public ::Kernel::Statistics {} }; -} /* end namespace ArmISA::Kernel */ -} /* end namespace ArmISA */ +} // namespace ArmISA::Kernel +} // namespace ArmISA #endif // __ARCH_ARM_KERNEL_STATS_HH__ diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 75546f8de..531a6ee2e 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -192,7 +192,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record) } } -} /* namespace Trace */ +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh index 7467e3378..221d40e2f 100644 --- a/src/arch/arm/nativetrace.hh +++ b/src/arch/arm/nativetrace.hh @@ -107,6 +107,6 @@ class ArmNativeTrace : public NativeTrace void check(NativeTraceRecord *record); }; -} /* namespace Trace */ +} // namespace Trace #endif // __ARCH_ARM_NATIVETRACE_HH__ diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 5b24eebe2..1374123b2 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -239,6 +239,6 @@ public: inline void invalidateMiscReg() { miscRegValid = false; } }; -/* namespace ArmISA */ } +} // namespace ArmISA #endif // __ARCH_ARM_TLB_HH__ diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh index a3d6c1a8f..1cca51384 100755 --- a/src/arch/mips/dsp.hh +++ b/src/arch/mips/dsp.hh @@ -199,6 +199,6 @@ void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign); void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask); uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask); -} /* namespace MipsISA */ +} // namespace MipsISA #endif // __ARCH_MIPS_DSP_HH__ diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 083aa5939..616886745 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -596,6 +596,6 @@ class DspStateDisabledFault : public MipsFault StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; -} // MipsISA namespace +} // namespace MipsISA #endif // __MIPS_FAULTS_HH__ diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index efb1fb594..648713926 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -39,7 +39,7 @@ #include "base/types.hh" #include "config/full_system.hh" -namespace LittleEndianGuest {}; +namespace LittleEndianGuest {} class StaticInstPtr; @@ -164,6 +164,6 @@ const uint32_t ITOUCH_ANNOTE = 0xffffffff; // Memory accesses cannot be unaligned const bool HasUnalignedMemAcc = false; -}; +} // namespace MipsISA #endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/src/arch/mips/kernel_stats.hh b/src/arch/mips/kernel_stats.hh index f14c6f851..5cf6087c8 100644 --- a/src/arch/mips/kernel_stats.hh +++ b/src/arch/mips/kernel_stats.hh @@ -48,7 +48,7 @@ class Statistics : public ::Kernel::Statistics }; -} /* end namespace MipsISA::Kernel */ -} /* end namespace MipsISA */ +} // namespace MipsISA::Kernel +} // namespace MipsISA #endif // __ARCH_MIPS_KERNEL_STATS_HH__ diff --git a/src/arch/mips/linux/threadinfo.hh b/src/arch/mips/linux/threadinfo.hh index b0d0cd811..20a4033dd 100644 --- a/src/arch/mips/linux/threadinfo.hh +++ b/src/arch/mips/linux/threadinfo.hh @@ -148,6 +148,6 @@ class ThreadInfo } }; -/* namespace Linux */ } +} // namespace Linux #endif // __ARCH_MIPS_LINUX_LINUX_THREADINFO_HH__ diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index 0f49cc85d..f1977150c 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -98,6 +98,6 @@ genMachineCheckFault() return new MachineCheckFault(); } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_FAULTS_HH__ diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh index 7b9e78dee..1947e4ec3 100644 --- a/src/arch/power/insts/branch.hh +++ b/src/arch/power/insts/branch.hh @@ -236,6 +236,6 @@ class BranchRegCond : public BranchCond std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_BRANCH_HH__ diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh index a23667d9e..e5112b2c1 100644 --- a/src/arch/power/insts/condition.hh +++ b/src/arch/power/insts/condition.hh @@ -81,6 +81,6 @@ class CondMoveOp : public PowerStaticInst std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_CONDITION_HH__ diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh index 2b2668409..deeac82cf 100644 --- a/src/arch/power/insts/floating.hh +++ b/src/arch/power/insts/floating.hh @@ -148,6 +148,6 @@ class FloatOp : public PowerStaticInst std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_FLOATING_HH__ diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index b4b96d5dc..a7270cd38 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -171,6 +171,6 @@ class IntRotateOp : public IntShiftOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_INTEGER_HH__ diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index 329dafe57..a58742690 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -86,6 +86,6 @@ class MemDispOp : public MemOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_MEM_HH__ diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh index dd4941b93..d6a73d254 100644 --- a/src/arch/power/insts/misc.hh +++ b/src/arch/power/insts/misc.hh @@ -52,6 +52,6 @@ class MiscOp : public PowerStaticInst std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_MISC_HH__ diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh index 91eca6fb0..48e5fa94b 100644 --- a/src/arch/power/insts/static_inst.hh +++ b/src/arch/power/insts/static_inst.hh @@ -71,6 +71,6 @@ class PowerStaticInst : public StaticInst } }; -} // PowerISA namespace +} // namespace PowerISA #endif //__ARCH_POWER_INSTS_STATICINST_HH__ diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index ba1b5018d..78ae18ea9 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -110,6 +110,6 @@ class ISA } }; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_ISA_HH__ diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh index ab6a56760..f0f50b9e9 100644 --- a/src/arch/power/isa_traits.hh +++ b/src/arch/power/isa_traits.hh @@ -38,7 +38,7 @@ #include "arch/power/types.hh" #include "base/types.hh" -namespace BigEndianGuest {}; +namespace BigEndianGuest {} class StaticInstPtr; @@ -73,6 +73,6 @@ const ExtMachInst NoopMachInst = 0x60000000; // Memory accesses can be unaligned const bool HasUnalignedMemAcc = true; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_ISA_TRAITS_HH__ diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh index 56ab1d4a0..6141b9ef2 100644 --- a/src/arch/power/locked_mem.hh +++ b/src/arch/power/locked_mem.hh @@ -59,6 +59,6 @@ handleLockedWrite(XC *xc, Request *req) return true; } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_LOCKED_MEM_HH__ diff --git a/src/arch/power/microcode_rom.hh b/src/arch/power/microcode_rom.hh index e35db5112..0cb100653 100644 --- a/src/arch/power/microcode_rom.hh +++ b/src/arch/power/microcode_rom.hh @@ -40,6 +40,6 @@ namespace PowerISA using ::MicrocodeRom; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_MICROCODE_ROM_HH__ diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh index 34732dad1..eba97d439 100644 --- a/src/arch/power/miscregs.hh +++ b/src/arch/power/miscregs.hh @@ -95,6 +95,6 @@ BitUnion32(Fpscr) Bitfield<2,1> rn; EndBitUnion(Fpscr) -}; // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_MISCREGS_HH__ diff --git a/src/arch/power/mmaped_ipr.hh b/src/arch/power/mmaped_ipr.hh index bd1ea10b3..fc88634dc 100644 --- a/src/arch/power/mmaped_ipr.hh +++ b/src/arch/power/mmaped_ipr.hh @@ -61,6 +61,6 @@ handleIprWrite(ThreadContext *xc, Packet *pkt) panic("No implementation for handleIprWrite in POWER\n"); } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_MMAPED_IPR_HH__ diff --git a/src/arch/power/pagetable.cc b/src/arch/power/pagetable.cc index 862404578..091fb8bc8 100644 --- a/src/arch/power/pagetable.cc +++ b/src/arch/power/pagetable.cc @@ -79,4 +79,4 @@ PTE::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(OffsetMask); } -} // PowerISA namespace +} // namespace PowerISA diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh index bd2b9d397..a5f18eba9 100644 --- a/src/arch/power/pagetable.hh +++ b/src/arch/power/pagetable.hh @@ -152,7 +152,7 @@ struct PTE void unserialize(Checkpoint *cp, const std::string §ion); }; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_PAGETABLE_H__ diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh index 431c5d1b7..8b1089095 100644 --- a/src/arch/power/predecoder.hh +++ b/src/arch/power/predecoder.hh @@ -120,6 +120,6 @@ class Predecoder } }; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_PREDECODER_HH__ diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index 59816a599..8b2aefc47 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -101,6 +101,6 @@ enum MiscIntRegNums { INTREG_RSV_ADDR }; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_REGISTERS_HH__ diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh index 34bb4bd1f..b37c31713 100644 --- a/src/arch/power/remote_gdb.hh +++ b/src/arch/power/remote_gdb.hh @@ -79,6 +79,6 @@ class RemoteGDB : public BaseRemoteGDB } }; -} // PowerISA namespace +} // namespace PowerISA #endif /* __ARCH_POWER_REMOTE_GDB_H__ */ diff --git a/src/arch/power/stacktrace.hh b/src/arch/power/stacktrace.hh index 49d687a6e..e87203df6 100644 --- a/src/arch/power/stacktrace.hh +++ b/src/arch/power/stacktrace.hh @@ -143,6 +143,6 @@ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) return true; } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_STACKTRACE_HH__ diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 8431b9ad1..7e5638cf1 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -167,6 +167,6 @@ class TLB : public BaseTLB void regStats(); }; -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_TLB_HH__ diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index d049cdec1..61f8acfca 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -101,6 +101,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> { }; }; -} // __hash_namespace namespace +} // namespace __hash_namespace #endif // __ARCH_POWER_TYPES_HH__ diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc index 399ec1f56..b02ccda08 100644 --- a/src/arch/power/utility.cc +++ b/src/arch/power/utility.cc @@ -62,4 +62,4 @@ skipFunction(ThreadContext *tc) } -} // PowerISA namespace +} // namespace PowerISA diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index a47fcdc46..cbb9bb646 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -78,6 +78,6 @@ advancePC(PCState &pc, const StaticInstPtr inst) pc.advance(); } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_UTILITY_HH__ diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh index 3cfebcfc7..8b88c9215 100644 --- a/src/arch/power/vtophys.hh +++ b/src/arch/power/vtophys.hh @@ -51,7 +51,7 @@ PteAddr(Addr a) return (a & PteMask) << PteShift; } -} // PowerISA namespace +} // namespace PowerISA #endif // __ARCH_POWER_VTOPHYS_HH__ diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index e10e07494..bee29ee5e 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -302,6 +302,6 @@ genMachineCheckFault() } -} // SparcISA namespace +} // namespace SparcISA #endif // __SPARC_FAULTS_HH__ diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh index c007c54c2..3d4c677a0 100644 --- a/src/arch/sparc/kernel_stats.hh +++ b/src/arch/sparc/kernel_stats.hh @@ -51,7 +51,7 @@ class Statistics : public ::Kernel::Statistics {} }; -} /* end namespace AlphaISA::Kernel */ -} /* end namespace AlphaISA */ +} // namespace AlphaISA::Kernel +} // namespace AlphaISA #endif // __ARCH_SPARC_KERNEL_STATS_HH__ diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc index 5e3d5c8b3..7d8b96dc1 100644 --- a/src/arch/sparc/nativetrace.cc +++ b/src/arch/sparc/nativetrace.cc @@ -87,7 +87,7 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record) checkReg("ccr", regVal, realRegVal); } -} /* namespace Trace */ +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/arch/sparc/nativetrace.hh b/src/arch/sparc/nativetrace.hh index d618107bb..0bd40712b 100644 --- a/src/arch/sparc/nativetrace.hh +++ b/src/arch/sparc/nativetrace.hh @@ -47,6 +47,6 @@ class SparcNativeTrace : public NativeTrace void check(NativeTraceRecord *record); }; -} /* namespace Trace */ +} // namespace Trace #endif // __CPU_NATIVETRACE_HH__ diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 512878499..7c7819561 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1408,7 +1408,7 @@ TLB::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(sfar); } -/* end namespace SparcISA */ } +} // namespace SparcISA SparcISA::TLB * SparcTLBParams::create() diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index 48e778c6f..36b2557e7 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -129,4 +129,4 @@ vtophys(ThreadContext *tc, Addr addr) return pte.translate(addr); } -} /* namespace SparcISA */ +} // namespace SparcISA diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc index 6b686f38a..fa5e30698 100644 --- a/src/arch/x86/cpuid.cc +++ b/src/arch/x86/cpuid.cc @@ -158,4 +158,4 @@ namespace X86ISA { } return true; } -} //namespace X86ISA +} // namespace X86ISA diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc index 6f92cfacf..1999f6611 100644 --- a/src/arch/x86/nativetrace.cc +++ b/src/arch/x86/nativetrace.cc @@ -186,7 +186,7 @@ X86NativeTrace::check(NativeTraceRecord *record) checkXMM(15, mState.xmm, nState.xmm); } -} /* namespace Trace */ +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/arch/x86/nativetrace.hh b/src/arch/x86/nativetrace.hh index afa2a463d..c68f01455 100644 --- a/src/arch/x86/nativetrace.hh +++ b/src/arch/x86/nativetrace.hh @@ -85,6 +85,6 @@ class X86NativeTrace : public NativeTrace void check(NativeTraceRecord *record); }; -} /* namespace Trace */ +} // namespace Trace #endif // __ARCH_X86_NATIVETRACE_HH__ diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index ea737fa63..5882132e5 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -111,6 +111,6 @@ typedef union typedef uint16_t RegIndex; -}; // namespace X86ISA +} // namespace X86ISA #endif // __ARCH_X86_REGFILE_HH__ diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 52d9cdf9c..7fa2e172c 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -737,7 +737,7 @@ TLB::unserialize(Checkpoint *cp, const std::string §ion) { } -/* end namespace X86ISA */ } +} // namespace X86ISA X86ISA::TLB * X86TLBParams::create() diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 88d5bfe58..756e9d526 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -243,4 +243,4 @@ skipFunction(ThreadContext *tc) } -} //namespace X86_ISA +} // namespace X86_ISA diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc index 5c11e501c..4f825c097 100644 --- a/src/base/cprintf.cc +++ b/src/base/cprintf.cc @@ -291,4 +291,4 @@ Print::end_args() stream.precision(saved_precision); } -/* end namespace cp */ } +} // namespace cp diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh index 2920e210d..cd5d642c1 100644 --- a/src/base/cprintf.hh +++ b/src/base/cprintf.hh @@ -125,7 +125,7 @@ struct Print void end_args(); }; -/* end namespace cp */ } +} // namespace cp typedef VarArgs::List<cp::Print> CPrintfArgsList; diff --git a/src/base/hashmap.hh b/src/base/hashmap.hh index eac1c6dc7..e3a72bcf5 100644 --- a/src/base/hashmap.hh +++ b/src/base/hashmap.hh @@ -92,6 +92,6 @@ namespace __hash_namespace { return (__stl_hash_string(r.first.c_str())) ^ r.second; } }; -/* namespace __hash_namespace */ } +} // namespace __hash_namespace #endif // __HASHMAP_HH__ diff --git a/src/base/inet.cc b/src/base/inet.cc index 3f804b01c..e4612c02d 100644 --- a/src/base/inet.cc +++ b/src/base/inet.cc @@ -297,4 +297,4 @@ hsplit(const EthPacketPtr &ptr) } -/* namespace Net */ } +} // namespace Net diff --git a/src/base/inet.hh b/src/base/inet.hh index b2a84e279..ecb088289 100644 --- a/src/base/inet.hh +++ b/src/base/inet.hh @@ -472,6 +472,6 @@ uint16_t cksum(const UdpPtr &ptr); int hsplit(const EthPacketPtr &ptr); -/* namespace Net */ } +} // namespace Net #endif // __BASE_INET_HH__ diff --git a/src/base/mysql.cc b/src/base/mysql.cc index 2416c766a..3216bcf43 100644 --- a/src/base/mysql.cc +++ b/src/base/mysql.cc @@ -109,4 +109,4 @@ Connection::query(const string &sql) } -/* namespace MySQL */ } +} // namespace MySQL diff --git a/src/base/mysql.hh b/src/base/mysql.hh index 272a0f07c..c9051bd2b 100644 --- a/src/base/mysql.hh +++ b/src/base/mysql.hh @@ -420,6 +420,6 @@ class Statement } #endif -/* namespace MySQL */ } +} // namespace MySQL #endif // __BASE_MYSQL_HH__ diff --git a/src/base/statistics.cc b/src/base/statistics.cc index 853f3a58d..1e108298a 100644 --- a/src/base/statistics.cc +++ b/src/base/statistics.cc @@ -377,4 +377,4 @@ registerResetCallback(Callback *cb) resetQueue.add(cb); } -/* namespace Stats */ } +} // namespace Stats diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 7eb769e43..3bb74282a 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2784,6 +2784,6 @@ void registerResetCallback(Callback *cb); std::list<Info *> &statsList(); -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATISTICS_HH__ diff --git a/src/base/stats/info.hh b/src/base/stats/info.hh index e5b9e4a65..421ed4a55 100644 --- a/src/base/stats/info.hh +++ b/src/base/stats/info.hh @@ -232,6 +232,6 @@ class FormulaInfo : public VectorInfo }; -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_INFO_HH__ diff --git a/src/base/stats/mysql.cc b/src/base/stats/mysql.cc index 9d2dadb01..d947122da 100644 --- a/src/base/stats/mysql.cc +++ b/src/base/stats/mysql.cc @@ -836,4 +836,4 @@ initMySQL(string host, string user, string password, string database, return true; } -/* end namespace Stats */ } +} // namespace Stats diff --git a/src/base/stats/mysql.hh b/src/base/stats/mysql.hh index 687f030f2..a09ee095c 100644 --- a/src/base/stats/mysql.hh +++ b/src/base/stats/mysql.hh @@ -179,6 +179,6 @@ initMySQL(std::string host, std::string user, std::string password, } #endif -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_MYSQL_HH__ diff --git a/src/base/stats/mysql_run.hh b/src/base/stats/mysql_run.hh index 7207cd841..29ca168dd 100644 --- a/src/base/stats/mysql_run.hh +++ b/src/base/stats/mysql_run.hh @@ -62,6 +62,6 @@ struct MySqlRun uint16_t run() const { return run_id; } }; -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_MYSQL_RUN_HH__ diff --git a/src/base/stats/output.cc b/src/base/stats/output.cc index ae2c9db5e..9d110e4ee 100644 --- a/src/base/stats/output.cc +++ b/src/base/stats/output.cc @@ -63,7 +63,7 @@ dump() } } -/* namespace Stats */ } +} // namespace Stats void debugDumpStats() diff --git a/src/base/stats/output.hh b/src/base/stats/output.hh index 4fe93791f..0f485dee3 100644 --- a/src/base/stats/output.hh +++ b/src/base/stats/output.hh @@ -44,6 +44,6 @@ struct Output : public Visit virtual bool valid() const = 0; }; -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_OUTPUT_HH__ diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc index 425a917ef..576f7e5d4 100644 --- a/src/base/stats/text.cc +++ b/src/base/stats/text.cc @@ -594,4 +594,4 @@ initText(const string &filename, bool desc) return true; } -/* namespace Stats */ } +} // namespace Stats diff --git a/src/base/stats/text.hh b/src/base/stats/text.hh index 0cb66ded8..ab8512859 100644 --- a/src/base/stats/text.hh +++ b/src/base/stats/text.hh @@ -75,6 +75,6 @@ class Text : public Output bool initText(const std::string &filename, bool desc); -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_TEXT_HH__ diff --git a/src/base/stats/types.hh b/src/base/stats/types.hh index 87cf91653..9faa8d33d 100644 --- a/src/base/stats/types.hh +++ b/src/base/stats/types.hh @@ -53,6 +53,6 @@ typedef std::vector<Result> VResult; typedef unsigned int size_type; typedef unsigned int off_type; -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_TYPES_HH__ diff --git a/src/base/stats/visit.cc b/src/base/stats/visit.cc index 6680eaa09..1d13bc25d 100644 --- a/src/base/stats/visit.cc +++ b/src/base/stats/visit.cc @@ -38,4 +38,4 @@ Visit::Visit() Visit::~Visit() {} -/* namespace Stats */ } +} // namespace Stats diff --git a/src/base/stats/visit.hh b/src/base/stats/visit.hh index f5c2fc34c..fae7a8883 100644 --- a/src/base/stats/visit.hh +++ b/src/base/stats/visit.hh @@ -55,6 +55,6 @@ struct Visit virtual void visit(const FormulaInfo &info) = 0; }; -/* namespace Stats */ } +} // namespace Stats #endif // __BASE_STATS_VISIT_HH__ diff --git a/src/base/stl_helpers.hh b/src/base/stl_helpers.hh index 9add7b8b6..a34ca7bb6 100644 --- a/src/base/stl_helpers.hh +++ b/src/base/stl_helpers.hh @@ -92,7 +92,7 @@ operator<<(std::ostream& out, const C<T,A> &vec) return out; } -/* namespace stl_helpers */ } -/* namespace m5 */ } +} // namespace stl_helpers +} // namespace m5 #endif // __BASE_STL_HELPERS_HH__ diff --git a/src/base/trace.cc b/src/base/trace.cc index 0a7e6e833..22e05e664 100644 --- a/src/base/trace.cc +++ b/src/base/trace.cc @@ -188,7 +188,7 @@ dumpStatus() } } -/* namespace Trace */ } +} // namespace Trace // add a set of functions that can easily be invoked from gdb diff --git a/src/base/trace.hh b/src/base/trace.hh index 6f8c196b0..f793abff9 100644 --- a/src/base/trace.hh +++ b/src/base/trace.hh @@ -60,7 +60,7 @@ void dprintf(Tick when, const std::string &name, const char *format, CPRINTF_DECLARATION); void dump(Tick when, const std::string &name, const void *data, int len); -/* namespace Trace */ } +} // namespace Trace // This silly little class allows us to wrap a string in a functor // object so that we can give a name() that DPRINTF will like diff --git a/src/base/varargs.hh b/src/base/varargs.hh index 4328f2057..87c98d006 100644 --- a/src/base/varargs.hh +++ b/src/base/varargs.hh @@ -303,6 +303,6 @@ class List } }; -/* end namespace VarArgs */ } +} // namespace VarArgs #endif /* __BASE_VARARGS_HH__ */ diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index f8b25ef73..760e5bd51 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -155,7 +155,7 @@ Trace::ExeTracerRecord::dump() } } -/* namespace Trace */ } +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index 65950728b..5dc65b48b 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -86,6 +86,6 @@ class ExeTracer : public InstTracer } }; -/* namespace Trace */ } +} // namespace Trace #endif // __CPU_EXETRACE_HH__ diff --git a/src/cpu/inorder/inorder_trace.cc b/src/cpu/inorder/inorder_trace.cc index 70a947671..75f6be63d 100644 --- a/src/cpu/inorder/inorder_trace.cc +++ b/src/cpu/inorder/inorder_trace.cc @@ -81,7 +81,7 @@ InOrderTrace::getInstRecord(Tick when, ThreadContext *tc, return new InOrderTraceRecord(ThePipeline::NumStages, true, tc, _pc); } -/* namespace Trace */ } +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/inorder/inorder_trace.hh b/src/cpu/inorder/inorder_trace.hh index fd1427500..5386f641d 100644 --- a/src/cpu/inorder/inorder_trace.hh +++ b/src/cpu/inorder/inorder_trace.hh @@ -93,6 +93,6 @@ class InOrderTrace : public InstTracer const StaticInstPtr macroStaticInst = NULL); }; -/* namespace Trace */ } +} // namespace Trace #endif // __CPU_INORDER_INORDER_TRACE_HH__ diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc index ee148c50f..0d1d003d1 100644 --- a/src/cpu/inteltrace.cc +++ b/src/cpu/inteltrace.cc @@ -57,7 +57,7 @@ Trace::IntelTraceRecord::dump() outs << endl; } -/* namespace Trace */ } +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh index 234b173e9..5083318ad 100644 --- a/src/cpu/inteltrace.hh +++ b/src/cpu/inteltrace.hh @@ -82,6 +82,6 @@ class IntelTrace : public InstTracer } }; -/* namespace Trace */ } +} // namespace Trace #endif // __CPU_INTELTRACE_HH__ diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index 8750e56e5..49b2f513c 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -587,7 +587,7 @@ Trace::LegionTraceRecord::dump() } // if not microop } -/* namespace Trace */ } +} // namespace Trace //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/legiontrace.hh b/src/cpu/legiontrace.hh index a60b9ad10..24957e40a 100644 --- a/src/cpu/legiontrace.hh +++ b/src/cpu/legiontrace.hh @@ -76,6 +76,6 @@ class LegionTrace : public InstTracer } }; -/* namespace Trace */ } +} // namespace Trace #endif // __CPU_LEGIONTRACE_HH__ diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index 8c17eb825..9660c0e13 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -62,4 +62,4 @@ Trace::NativeTraceRecord::dump() parent->check(this); } -} /* namespace Trace */ +} // namespace Trace diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 5c5b9a66d..cc388d6bf 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -119,6 +119,6 @@ class NativeTrace : public ExeTracer check(NativeTraceRecord *record) = 0; }; -} /* namespace Trace */ +} // namespace Trace #endif // __CPU_NATIVETRACE_HH__ diff --git a/src/dev/copy_engine_defs.hh b/src/dev/copy_engine_defs.hh index 16bf57d58..98216e64c 100644 --- a/src/dev/copy_engine_defs.hh +++ b/src/dev/copy_engine_defs.hh @@ -220,6 +220,6 @@ struct ChanRegs { }; -} //namespace CopyEngineReg +} // namespace CopyEngineReg diff --git a/src/dev/i8254xGBe_defs.hh b/src/dev/i8254xGBe_defs.hh index c37a6dc0e..71a7c16da 100644 --- a/src/dev/i8254xGBe_defs.hh +++ b/src/dev/i8254xGBe_defs.hh @@ -851,4 +851,4 @@ struct Regs { UNSERIALIZE_SCALAR(sw_fw_sync); } }; -} // iGbReg namespace +} // namespace iGbReg diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 86090e048..2183d9d99 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1714,7 +1714,7 @@ Device::unserialize(Checkpoint *cp, const std::string §ion) } -/* namespace Sinic */ } +} // namespace Sinic Sinic::Device * SinicParams::create() diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index d2124d8ce..0da7ccae4 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -349,6 +349,6 @@ class Interface : public EtherInt virtual void sendDone() { dev->transferDone(); } }; -/* namespace Sinic */ } +} // namespace Sinic #endif // __DEV_SINIC_HH__ diff --git a/src/dev/sinicreg.hh b/src/dev/sinicreg.hh index 7ac7abad0..43dc46dc4 100644 --- a/src/dev/sinicreg.hh +++ b/src/dev/sinicreg.hh @@ -178,7 +178,7 @@ struct Info const char *name; }; -/* namespace Regs */ } +} // namespace Regs inline const Regs::Info& regInfo(Addr daddr) @@ -234,6 +234,6 @@ regValid(Addr daddr) return true; } -/* namespace Sinic */ } +} // namespace Sinic #endif // __DEV_SINICREG_HH__ diff --git a/src/dev/x86/cmos.hh b/src/dev/x86/cmos.hh index 76276dbc1..22cd9e3af 100644 --- a/src/dev/x86/cmos.hh +++ b/src/dev/x86/cmos.hh @@ -84,6 +84,6 @@ class Cmos : public BasicPioDevice Tick write(PacketPtr pkt); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_CMOS_HH__ diff --git a/src/dev/x86/i8042.hh b/src/dev/x86/i8042.hh index 8a941f9a5..7aa59e9a7 100644 --- a/src/dev/x86/i8042.hh +++ b/src/dev/x86/i8042.hh @@ -254,6 +254,6 @@ class I8042 : public BasicPioDevice Tick write(PacketPtr pkt); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_I8042_HH__ diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh index c3a832aa9..70717f6ba 100644 --- a/src/dev/x86/i82094aa.hh +++ b/src/dev/x86/i82094aa.hh @@ -132,6 +132,6 @@ class I82094AA : public PioDevice, public IntDev void registerLocalApic(int id, Interrupts *localApic); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__ diff --git a/src/dev/x86/i8237.hh b/src/dev/x86/i8237.hh index 2d73b8ab5..1db91236a 100644 --- a/src/dev/x86/i8237.hh +++ b/src/dev/x86/i8237.hh @@ -61,6 +61,6 @@ class I8237 : public BasicPioDevice Tick write(PacketPtr pkt); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_I8237_HH__ diff --git a/src/dev/x86/i8254.hh b/src/dev/x86/i8254.hh index 7de20dfd4..e295f5105 100644 --- a/src/dev/x86/i8254.hh +++ b/src/dev/x86/i8254.hh @@ -111,6 +111,6 @@ class I8254 : public BasicPioDevice } }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__ diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh index a9c5baa8c..a9362d403 100644 --- a/src/dev/x86/i8259.hh +++ b/src/dev/x86/i8259.hh @@ -110,6 +110,6 @@ class I8259 : public BasicPioDevice, public IntDev int getVector(); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_I8259_HH__ diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh index 8f5f8707e..b01d36e37 100644 --- a/src/dev/x86/intdev.hh +++ b/src/dev/x86/intdev.hh @@ -234,6 +234,6 @@ class IntLine : public SimObject } }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_INTDEV_HH__ diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh index 6778dcb28..fb7476ca0 100644 --- a/src/dev/x86/speaker.hh +++ b/src/dev/x86/speaker.hh @@ -74,6 +74,6 @@ class Speaker : public BasicPioDevice Tick write(PacketPtr pkt); }; -}; // namespace X86ISA +} // namespace X86ISA #endif //__DEV_X86_SPEAKER_HH__ diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc index 29c77b3d9..aa9342a13 100644 --- a/src/kern/kernel_stats.cc +++ b/src/kern/kernel_stats.cc @@ -139,4 +139,4 @@ Statistics::unserialize(Checkpoint *cp, const string §ion) UNSERIALIZE_SCALAR(iplLastTick); } -/* end namespace Kernel */ } +} // namespace Kernel diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh index cd3c12d47..5395b3337 100644 --- a/src/kern/kernel_stats.hh +++ b/src/kern/kernel_stats.hh @@ -85,6 +85,6 @@ class Statistics : public Serializable virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -/* end namespace Kernel */ } +} // namespace Kernel #endif // __KERNEL_STATS_HH__ diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index 23b683d69..89e1929a0 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -277,7 +277,7 @@ template <> struct hash<Address> return (size_t)s.getAddress(); } }; -/* namespace __hash_namespace */ } +} // namespace __hash_namespace namespace std { template <> struct equal_to<Address> @@ -288,6 +288,6 @@ template <> struct equal_to<Address> return s1 == s2; } }; -/* namespace std */ } +} // namespace std #endif // __MEM_RUBY_COMMON_ADDRESS_HH__ diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 710f85fde..00c18976d 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -126,7 +126,7 @@ def default_swig_objdecls(cls, code): code('{};') for ns in reversed(namespaces): - code('/* namespace $ns */ }') + code('} // namespace $ns') def public_value(key, value): return key.startswith('_') or \ @@ -390,7 +390,7 @@ class MetaSimObject(type): code('namespace $ns {') code('class $0;', class_path[-1]) for ns in reversed(class_path[:-1]): - code('/* namespace $ns */ }') + code('} // namespace $ns') code() for param in params: diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 0093a411d..2c3925d99 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -1004,7 +1004,7 @@ namespace Enums { code.dedent(2) code(''' }; -/* namespace Enums */ } +} // namespace Enums ''') # Base class for enum types. diff --git a/src/python/swig/stats.i b/src/python/swig/stats.i index fc4a83394..eaa4c31c8 100644 --- a/src/python/swig/stats.i +++ b/src/python/swig/stats.i @@ -59,4 +59,4 @@ void reset(); std::list<Info *> &statsList(); -/* namespace Stats */ } +} // namespace Stats diff --git a/src/sim/core.cc b/src/sim/core.cc index 32642c8a4..1b7a034f0 100644 --- a/src/sim/core.cc +++ b/src/sim/core.cc @@ -55,7 +55,7 @@ double Hz; double kHz; double MHz; double GHZ; -/* namespace Float */ } +} // namespace Float namespace Int { Tick s; @@ -63,9 +63,9 @@ Tick ms; Tick us; Tick ns; Tick ps; -/* namespace Float */ } +} // namespace Float -/* namespace SimClock */ } +} // namespace SimClock void setClockFrequency(Tick ticksPerSecond) diff --git a/src/sim/core.hh b/src/sim/core.hh index 8be1dd259..074ce32b6 100644 --- a/src/sim/core.hh +++ b/src/sim/core.hh @@ -55,7 +55,7 @@ extern double Hz; extern double kHz; extern double MHz; extern double GHZ; -/* namespace Float */ } +} // namespace Float namespace Int { extern Tick s; @@ -63,8 +63,8 @@ extern Tick ms; extern Tick us; extern Tick ns; extern Tick ps; -/* namespace Int */ } -/* namespace SimClock */ } +} // namespace Int +} // namespace SimClock void setClockFrequency(Tick ticksPerSecond); diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh index 1ff67d2cb..2afea07ea 100644 --- a/src/sim/insttracer.hh +++ b/src/sim/insttracer.hh @@ -170,6 +170,6 @@ class InstTracer : public SimObject -}; // namespace Trace +} // namespace Trace #endif // __INSTRECORD_HH__ diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 7a91bfbd4..683397116 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -326,4 +326,4 @@ switchcpu(ThreadContext *tc) exitSimLoop("switchcpu"); } -/* namespace PseudoInst */ } +} // namespace PseudoInst diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 847dcede0..2f9671155 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -64,4 +64,4 @@ void m5checkpoint(ThreadContext *tc, Tick delay, Tick period); void debugbreak(ThreadContext *tc); void switchcpu(ThreadContext *tc); -/* namespace PseudoInst */ } +} // namespace PseudoInst diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 07e1b2380..83861c185 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -201,4 +201,4 @@ StatEvent(bool dump, bool reset, Tick when, Tick repeat) mainEventQueue.schedule(event, when); } -/* namespace Stats */ } +} // namespace Stats diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh index 1efa2554e..78031b666 100644 --- a/src/sim/stat_control.hh +++ b/src/sim/stat_control.hh @@ -36,6 +36,6 @@ namespace Stats { void initSimStats(); void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0); -/* namespace Stats */ } +} // namespace Stats #endif // __SIM_STAT_CONTROL_HH__ |