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authorSteve Reinhardt <stever@eecs.umich.edu>2006-06-10 00:22:42 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-06-10 00:22:42 -0400
commitcd6550473957258130a549ef74e2f18102b8c881 (patch)
tree4330f082c66906c78f94a25143bbc1370a736a41 /src
parentf693b451a59949ef1a025fe8b391031d2234f1e1 (diff)
downloadgem5-cd6550473957258130a549ef74e2f18102b8c881.tar.xz
Update scripts for testing ALPHA_FS and MIPS_SE.
Minor fixes to ALPHA_FS and SPARC_SE. SPARC_SE still does not compile... looks like there are unresolved issues with ExecContext -> ThreadContext rename/reorg. configs/test/fs.py: Port to new script interface/model. configs/test/test.py: Add support for running MIPS test(s) too via command-line option. src/arch/alpha/ev5.cc: Fix include file. src/arch/sparc/regfile.hh: Make Bit64 a ULL constant to avoid compiler error. --HG-- extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624
Diffstat (limited to 'src')
-rw-r--r--src/arch/alpha/ev5.cc2
-rw-r--r--src/arch/sparc/regfile.hh3
2 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index dddefeb28..7d6894733 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -41,7 +41,7 @@
#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#include "sim/debug.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
#if FULL_SYSTEM
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index aaf1fcf24..760edc41e 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -61,8 +61,7 @@ namespace SparcISA
const int HprStart = 64;
const int MiscStart = 96;
-
- const uint64_t Bit64 = 0x8000000000000000;
+ const uint64_t Bit64 = (1ULL << 63);
class IntRegFile
{