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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
commitdbee6e0c5406200066b8185fd38fa47dae7cdd2f (patch)
treecc1cb169d8a215010d2adbf1b4eea82d70fa695a /src
parent239c9af90d61b2877a8cee8b91f162e7a0bf1e72 (diff)
downloadgem5-dbee6e0c5406200066b8185fd38fa47dae7cdd2f.tar.xz
ARM: Add a base class for SRS.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/insts/mem.cc55
-rw-r--r--src/arch/arm/insts/mem.hh24
-rw-r--r--src/arch/arm/isa/templates/mem.isa30
3 files changed, 109 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 394c159d1..eb16e42d0 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -87,6 +87,61 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
+string
+SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ switch (mode) {
+ case DecrementAfter:
+ printMnemonic(ss, "da");
+ break;
+ case DecrementBefore:
+ printMnemonic(ss, "db");
+ break;
+ case IncrementAfter:
+ printMnemonic(ss, "ia");
+ break;
+ case IncrementBefore:
+ printMnemonic(ss, "ib");
+ break;
+ }
+ printReg(ss, INTREG_SP);
+ if (wb) {
+ ss << "!";
+ }
+ ss << ", #";
+ switch (mode) {
+ case MODE_USER:
+ ss << "user";
+ break;
+ case MODE_FIQ:
+ ss << "fiq";
+ break;
+ case MODE_IRQ:
+ ss << "irq";
+ break;
+ case MODE_SVC:
+ ss << "supervisor";
+ break;
+ case MODE_MON:
+ ss << "monitor";
+ break;
+ case MODE_ABORT:
+ ss << "abort";
+ break;
+ case MODE_UNDEFINED:
+ ss << "undefined";
+ break;
+ case MODE_SYSTEM:
+ ss << "system";
+ break;
+ default:
+ ss << "unrecognized";
+ break;
+ }
+ return ss.str();
+}
+
void
Memory::printInst(std::ostream &os, AddrMode addrMode) const
{
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index ae3437120..50f718b99 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -87,6 +87,30 @@ class RfeOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+// The address is a base register plus an immediate.
+class SrsOp : public PredOp
+{
+ public:
+ enum AddrMode {
+ DecrementAfter,
+ DecrementBefore,
+ IncrementAfter,
+ IncrementBefore
+ };
+ protected:
+ uint32_t regMode;
+ AddrMode mode;
+ bool wb;
+
+ SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ uint32_t _regMode, AddrMode _mode, bool _wb)
+ : PredOp(mnem, _machInst, __opClass),
+ regMode(_regMode), mode(_mode), wb(_wb)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class Memory : public PredOp
{
public:
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 7c93cd4ee..983d99af9 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -409,6 +409,26 @@ def template RfeDeclare {{
};
}};
+def template SrsDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst,
+ uint32_t _regMode, int _mode, bool _wb);
+
+ %(BasicExecDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
+}};
+
def template SwapDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -575,6 +595,16 @@ def template RfeConstructor {{
}
}};
+def template SrsConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ uint32_t _regMode, int _mode, bool _wb)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ (OperatingMode)_regMode, (AddrMode)_mode, _wb)
+ {
+ %(constructor)s;
+ }
+}};
+
def template SwapConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base)