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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
commitec4cd00b1101d7436ff2019dfc9fc1c09442c9c9 (patch)
tree9bf1a2f687e2103d6f099a0e421a641717b3b45a /src
parent1ada9d48802ad2bccb1c1d9269797778198038fd (diff)
downloadgem5-ec4cd00b1101d7436ff2019dfc9fc1c09442c9c9.tar.xz
ARM: Add a base class for the RFE instruction.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/insts/mem.cc25
-rw-r--r--src/arch/arm/insts/mem.hh24
-rw-r--r--src/arch/arm/isa/templates/mem.isa30
3 files changed, 79 insertions, 0 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 521499847..394c159d1 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -62,6 +62,31 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
+string
+RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ switch (mode) {
+ case DecrementAfter:
+ printMnemonic(ss, "da");
+ break;
+ case DecrementBefore:
+ printMnemonic(ss, "db");
+ break;
+ case IncrementAfter:
+ printMnemonic(ss, "ia");
+ break;
+ case IncrementBefore:
+ printMnemonic(ss, "ib");
+ break;
+ }
+ printReg(ss, base);
+ if (wb) {
+ ss << "!";
+ }
+ return ss.str();
+}
+
void
Memory::printInst(std::ostream &os, AddrMode addrMode) const
{
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index dc4b7d627..d5b5d3519 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -63,6 +63,30 @@ class Swap : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+// The address is a base register plus an immediate.
+class RfeOp : public PredOp
+{
+ public:
+ enum AddrMode {
+ DecrementAfter,
+ DecrementBefore,
+ IncrementAfter,
+ IncrementBefore
+ };
+ protected:
+ IntRegIndex base;
+ AddrMode mode;
+ bool wb;
+
+ RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _base, AddrMode _mode, bool _wb)
+ : PredOp(mnem, _machInst, __opClass),
+ base(_base), mode(_mode), wb(_wb)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class Memory : public PredOp
{
public:
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 6e76b07c1..e44fe41db 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -294,6 +294,26 @@ def template StoreCompleteAcc {{
}
}};
+def template RfeDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst,
+ uint32_t _base, int _mode, bool _wb);
+
+ %(BasicExecDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
+}};
+
def template SwapDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -408,6 +428,16 @@ def template CompleteAccDeclare {{
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
+def template RfeConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ uint32_t _base, int _mode, bool _wb)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ (IntRegIndex)_base, (AddrMode)_mode, _wb)
+ {
+ %(constructor)s;
+ }
+}};
+
def template SwapConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base)