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| author | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2016-04-15 10:03:03 -0500 |
|---|---|---|
| committer | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2016-04-15 10:03:03 -0500 |
| commit | edbf748181bdd3ac86838e7c55d98a336b285e01 (patch) | |
| tree | a5109887d27849f1b45af582a2021f63bc8649df /src | |
| parent | bc45e930e4d7368a21270767e3530aa8f3306a93 (diff) | |
| download | gem5-edbf748181bdd3ac86838e7c55d98a336b285e01.tar.xz | |
arm,dev: remove PMU assertion hit on reset
Remve the assertion that we always need to add a delta larger than
zero as that does not seem to be true when we hit it in the
'PMU reset cycle counter to zero' case.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/pmu.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 6ea053e55..39530702c 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -574,8 +574,6 @@ PMU::CounterState::add(uint64_t delta) const uint64_t msb(1ULL << (overflow64 ? 63 : 31)); const uint64_t old_value(value); - assert(delta > 0); - value += delta; // Overflow if the msb goes from 1 to 0 |