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authorSteve Reinhardt <steve.reinhardt@amd.com>2015-02-11 10:48:50 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2015-02-11 10:48:50 -0800
commitee0b52404c99cfed91a8d3fbebe3f42b0ac133df (patch)
tree5c26f8de53e57903f80ed45e643b4abd3020040a /src
parentccef61d1ccaea43cf44aa45bee272475f0b10405 (diff)
downloadgem5-ee0b52404c99cfed91a8d3fbebe3f42b0ac133df.tar.xz
mem: restructure Packet cmd initialization a bit more
Refactor the way that specific MemCmd values are generated for packets. The new approach is a little more elegant in that we assign the right value up front, and it's also more amenable to non-heap-allocated Packet objects. Also replaced the code in the Minor model that was still doing it the ad-hoc way. This is basically a refinement of http://repo.gem5.org/gem5/rev/711eb0e64249.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc13
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh4
-rw-r--r--src/cpu/minor/lsq.cc14
-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/mem/packet.hh50
5 files changed, 41 insertions, 43 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index f8fa3b0d3..78b803501 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -811,10 +811,17 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
void
CacheUnit::buildDataPacket(CacheRequest *cache_req)
{
- cache_req->dataPkt = new CacheReqPacket(cache_req,
- cache_req->pktCmd,
+ MemCmd cmd;
+
+ if (cache_req->pktCmd == MemCmd::ReadReq) {
+ cmd = Packet::makeReadCmd(cache_req->memReq);
+ } else {
+ assert(cache_req->pktCmd == MemCmd::WriteReq);
+ cmd = Packet::makeWriteCmd(cache_req->memReq);
+ }
+
+ cache_req->dataPkt = new CacheReqPacket(cache_req, cmd,
cache_req->instIdx);
- cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 65f18eedb..11eb9ddad 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -230,7 +230,7 @@ class CacheRequest : public ResourceRequest
bool isMemAccPending() { return memAccPending; }
//Make this data private/protected!
- MemCmd::Command pktCmd;
+ MemCmd pktCmd;
RequestPtr memReq;
PacketDataPtr reqData;
CacheReqPacket *dataPkt;
@@ -252,7 +252,7 @@ class CacheReqPacket : public Packet
{
public:
CacheReqPacket(CacheRequest *_req,
- Command _cmd, int _idx = 0)
+ MemCmd _cmd, int _idx = 0)
: Packet(&(*_req->memReq), _cmd), cacheReq(_req),
instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
{
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 06b6c5165..ff609deac 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1545,18 +1545,8 @@ PacketPtr
makePacketForRequest(Request &request, bool isLoad,
Packet::SenderState *sender_state, PacketDataPtr data)
{
- MemCmd command;
-
- /* Make a ret with the right command type to match the request */
- if (request.isLLSC()) {
- command = (isLoad ? MemCmd::LoadLockedReq : MemCmd::StoreCondReq);
- } else if (request.isSwap()) {
- command = MemCmd::SwapReq;
- } else {
- command = (isLoad ? MemCmd::ReadReq : MemCmd::WriteReq);
- }
-
- PacketPtr ret = new Packet(&request, command);
+ PacketPtr ret = isLoad ? Packet::createRead(&request)
+ : Packet::createWrite(&request);
if (sender_state)
ret->pushSenderState(sender_state);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b564521ba..007621feb 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -341,8 +341,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt(req, MemCmd::ReadReq);
- pkt.refineCommand();
+ Packet pkt(req, Packet::makeReadCmd(req));
pkt.dataStatic(data);
if (req->isMmappedIpr())
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index cb8a5cbf4..8badc7c73 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -643,45 +643,47 @@ class Packet : public Printable
}
/**
- * Change the packet type based on request type.
+ * Generate the appropriate read MemCmd based on the Request flags.
*/
- void
- refineCommand()
+ static MemCmd
+ makeReadCmd(const RequestPtr req)
{
- if (cmd == MemCmd::ReadReq) {
- if (req->isLLSC()) {
- cmd = MemCmd::LoadLockedReq;
- } else if (req->isPrefetch()) {
- cmd = MemCmd::SoftPFReq;
- }
- } else if (cmd == MemCmd::WriteReq) {
- if (req->isLLSC()) {
- cmd = MemCmd::StoreCondReq;
- } else if (req->isSwap()) {
- cmd = MemCmd::SwapReq;
- }
- }
+ if (req->isLLSC())
+ return MemCmd::LoadLockedReq;
+ else if (req->isPrefetch())
+ return MemCmd::SoftPFReq;
+ else
+ return MemCmd::ReadReq;
+ }
+
+ /**
+ * Generate the appropriate write MemCmd based on the Request flags.
+ */
+ static MemCmd
+ makeWriteCmd(const RequestPtr req)
+ {
+ if (req->isLLSC())
+ return MemCmd::StoreCondReq;
+ else if (req->isSwap())
+ return MemCmd::SwapReq;
+ else
+ return MemCmd::WriteReq;
}
/**
* Constructor-like methods that return Packets based on Request objects.
- * Will call refineCommand() to fine-tune the Packet type if it's not a
- * vanilla read or write.
+ * Fine-tune the MemCmd type if it's not a vanilla read or write.
*/
static PacketPtr
createRead(const RequestPtr req)
{
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
- pkt->refineCommand();
- return pkt;
+ return new Packet(req, makeReadCmd(req));
}
static PacketPtr
createWrite(const RequestPtr req)
{
- PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
- pkt->refineCommand();
- return pkt;
+ return new Packet(req, makeWriteCmd(req));
}
/**