The palcode will now build by simply typing make in this directory.

Most of the changes were to fix broken macros in platfrom_tlaser.s

palcode/Makefile:
    Completly new makefile to build palcode
palcode/ev5_alpha_defs.h:
    fixed a broken define
palcode/ev5_impure.h:
    macro fixes
palcode/platform_srcmax.s:
    manual macro expansion of broken macros... this file isn't needed to
    build tlaser palcode
palcode/platform_tlaser.s:
    lots of fixups to make the code assemble

6 files changed, 350 insertions, 200 deletions

diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile
index 7d4f21cd1..416d347dc 100644
--- a/system/alpha/palcode/Makefile
+++ b/system/alpha/palcode/Makefile
@@ -1,157 +1,29 @@
-# 
-# $Id: Makefile,v 1.2 1997/12/16 01:18:38 bugnion Exp $
-#
-# Revision History:
-#
-# $Log: Makefile,v $
-# Revision 1.2  1997/12/16 01:18:38  bugnion
-# Removed bogus TLASER offsets from palcode build. -- roll over
-# simultaneously with the simulation tree
-#
-# Revision 1.1.1.1  1997/10/30 23:27:18  verghese
-# current 10/29/97
-#
-#
-# Set environment variables to point to various things:
-#
-#	EB_TOOLBOX - Where your toolset is located
-#
+#Makefile for palcode
+#Works on alpha-linux and builds elf executable
 
-EB_TOOLBOX =  /wrl/proj/simos/bin/tools/osf
-CPP	  =	/usr/bin/cpp
-AS	  =	$(EB_TOOLBOX)/gas
-LD	  =	$(EB_TOOLBOX)/gld
-DIS	  =	$(EB_TOOLBOX)/alist
-STRIP	  =	$(EB_TOOLBOX)/astrip
-PVC	  =	$(EB_TOOLBOX)/pvc
-MAKEDEP	  =	$(CPP) -MM
+#19 December 2003 - Ali Saidi
 
-#
-# Define KDEBUG if you want a special unprivileged CALL_PAL 
-# breakpoint trap handler for remote kernel debugging.
-#
-# Define CONSOLE_ENTRY to change the sys$enter_console
-# transfer address.  Default CONSOLE_ENTRY value is 0x10000.
-#
-# Define DISABLE_CRD to disable CRD. Note that reset sets MCES so that
-# correctable errors are ignored anyway, but this actually stops the
-# interrupt.
-#
+GAS = as
+CC = g++
+LD = ld
+#CFLAGS=-I ../h -E -P -D SIMOS -nostdinc -nostdinc++ -x c++
+CFLAGS=-I . -E -P -D SIMOS -D BUILD_PALCODE -nostdinc -nostdinc++ -x c++
+GASFLAGS=-m21164
+LDFLAGS=-Ttext 0x4000
 
-DEFINES   =	 -DDISABLE_CRD -DSIMOS -DBUILD_PALCODE
-DEFINES  +=  -I$(SIMTOOLS)/cpus-alpha/simos
+SOURCES=platform_tlaser.s osfpal.s
+PREPROC := $(SOURCES:.s=.i)
+OBJS := $(SOURCES:.s=.o)
+    
+%.i: %.s
+	$(CC) $(CFLAGS) $< > $@
 
-CPPFLAGS  =
-ASFLAGS   =	-21164
-#LDFLAGS   =	-Tstrip 0 -Thdr -N
-#LDFLAGS   =	-Tstrip 2000 -Thdr -N  # removed bugnion
-LDFLAGS   =	-Tstrip 4000 -Thdr -N
-# Source files:
-#
-#   This is the only block in which the list of source files should change.
-#
-#	SFILES - assembler source files
-#	HFILES - header files
-#
+%.o: %.i
+	$(GAS) $(GASFLAGS) -o $@ $< 
 
-SFILES	= osfpal.s platform.s
 
-HFILES	= dc21164.h \
-	  osf.h \
-	  macros.h \
-	  ev5_impure.h \
-	  cserve.h \
-	  platform.h
-
-# Intermediate files:
-#
-#   This block should not change.
-#
-
-IFILES	= $(SFILES:.s=.i)
-
-# Object files:
-#
-#   This block should not change.
-#
-
-OFILES 	= $(IFILES:.i=.o)
-
-.DEFAULT:
-	co -u $<
-
-.SUFFIXES:
-.SUFFIXES: .s .i .o
-
-.s.i:
-	$(CPP) $(CPPFLAGS) $(DEFINES) $< $*.i
-
-osfpal.nh: osfpal
-	$(STRIP) -a osfpal $@
-	$(DIS) osfpal >osfpal.dis
-
-osfpal: $(OFILES)
-	echo '$OFILES= ' $(OFILES)
-	$(LD) $(LDFLAGS) -o $@ $(OFILES)
-
-osfpal.o: osfpal.i
-	$(AS) $(ASFLAGS) -o $@ osfpal.i
-
-platform.o: platform.i
-	$(AS) $(ASFLAGS)  -o $@ platform.i
-
-pvc: osfpal.lis osfpal.nh osfpal.ent osfpal.map
-	(export PVC_PAL PVC_ENTRY PVC_MAP PVC_CPU;	\
-	 PVC_PAL=osfpal.nh;				\
-	 PVC_ENTRY=osfpal.ent;				\
-	 PVC_MAP=osfpal.map;				\
-	 PVC_CPU=ev5;					\
-	 $(PVC);)
-
-osfpal.lis: osfpal
-	$(DIS) osfpal > $@
-
-osfpal.map: osfpal
-	$(DIS) -m osfpal > $@
-	
-depend:
-	@cat < /dev/null > makedep
-	@(for i in $(SFILES); do echo $$i; \
-	    $(MAKEDEP) $(DEFINES) $$i | 					\
-		awk '{ if ($$1 != prev) {if (rec != "") print rec; 		\
-		    rec = $$0; prev = $$1; } 					\
-		    else { if (length(rec $$2) > 78) { print rec; rec = $$0; } 	\
-		    else rec = rec " " $$2 } }		 			\
-		    END { print rec }' | sed 's/\.o/\.i/'			\
-		    >> makedep; done)
-	@echo '/^# DO NOT DELETE THIS LINE/+1,$$d' > eddep
-	@echo '$$r makedep' >> eddep
-	@echo 'w' >> eddep
-	@cp Makefile Makefile.bak
-	@ed - Makefile < eddep
-	@rm -f eddep makedep
-	@echo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile
-	@echo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile
-	@echo '# see make depend above' >> Makefile
+all: $(PREPROC) $(OBJS)
+	ld $(LDFLAGS) -o osfpal $(OBJS) 
 
 clean:
-	rm -f core $(OFILES) $(IFILES)
-
-clobber: clean
-	rm -f osfpal.lis osfpal.nh osfpal.map osfpal
-
-rcsinfo:
-	rlog RCS/*
-
-rcsget:
-	co -u $(HFILES) $(SFILES)
-
-# DO NOT DELETE THIS LINE
-osfpal.i:	osfpal.s
-platform.i:	platform.s ./cserve.h ./platform.h
-# DEPENDENCIES MUST END AT END OF FILE
-# IF YOU PUT STUFF HERE IT WILL GO AWAY
-# see make depend above
-
-
-
+	rm -f *.o *.i osfpal
diff --git a/system/alpha/palcode/ev5_alpha_defs.h b/system/alpha/palcode/ev5_alpha_defs.h
index 33dc3c57a..96769de04 100644
--- a/system/alpha/palcode/ev5_alpha_defs.h
+++ b/system/alpha/palcode/ev5_alpha_defs.h
@@ -314,7 +314,7 @@
 #define mces_m_pce               (1<<mces_v_pce)
 #define mces_m_dpc               (1<<mces_v_dpc)
 #define mces_m_dsc               (1<<mces_v_dsc)
-#define mces_m_all		 ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) ! (1<<mces_v_dsc))
+#define mces_m_all		 ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc))
 //	_defend	mces,_gbl,def
 //	.endm
 
diff --git a/system/alpha/palcode/ev5_impure.h b/system/alpha/palcode/ev5_impure.h
index 84d700c32..ffa910ce2 100644
--- a/system/alpha/palcode/ev5_impure.h
+++ b/system/alpha/palcode/ev5_impure.h
@@ -51,7 +51,7 @@
 ** macros will auto-magically adjust the offsets accordingly.
 **
 */
-
+#if 0
 #define SAVE_GPR(reg,offset,base) \
         stq_p	reg, ((offset-0x200)&0x3FF)(base)
 
@@ -78,7 +78,38 @@
 
 #define	RESTORE_SHADOW(reg,offset,base)\
         ldq_p	reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
+#else
+//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
+#define SEXT10(X) ((X) & 0x3ff)
+//#define SEXT10(X) (((X) << 55) >> 55)
+
+#define SAVE_GPR(reg,offset,base) \
+        stq_p	reg, (SEXT10(offset-0x200))(base)
+
+#define RESTORE_GPR(reg,offset,base) \
+        ldq_p	reg, (SEXT10(offset-0x200))(base)
+
+
+#define SAVE_FPR(reg,offset,base) \
+        stt	reg, (SEXT10(offset-0x200))(base)
+
+#define RESTORE_FPR(reg,offset,base) \
+        ldt	reg, (SEXT10(offset-0x200))(base)
 
+#define SAVE_IPR(reg,offset,base) \
+        mfpr	v0, reg;	  \
+        stq_p	v0, (SEXT10(offset-CNS_Q_IPR))(base)
+
+#define RESTORE_IPR(reg,offset,base) \
+        ldq_p	v0, (SEXT10(offset-CNS_Q_IPR))(base); \
+        mtpr	v0, reg
+
+#define SAVE_SHADOW(reg,offset,base) \
+        stq_p	reg, (SEXT10(offset-CNS_Q_IPR))(base)
+
+#define	RESTORE_SHADOW(reg,offset,base)\
+        ldq_p	reg, (SEXT10(offset-CNS_Q_IPR))(base)
+#endif
 /* orig  Structure of the processor-specific impure area */
 
 /* orig aggregate impure struct prefix "" tag "";
diff --git a/system/alpha/palcode/platform_srcmax.s b/system/alpha/palcode/platform_srcmax.s
index b74573132..3e3a7c16b 100644
--- a/system/alpha/palcode/platform_srcmax.s
+++ b/system/alpha/palcode/platform_srcmax.s
@@ -1258,14 +1258,33 @@ sys_mchk_write_logout_frame:
 	mfpr	r25, regName ; \
 	stqp	r25, CNS_Q_/**/regOff(r14)
 
-	mchk_logout(mm_stat, MM_STAT)
-	mchk_logout(va, VA)			// Unlocks VA and MM_STAT
-	mchk_logout(isr, ISR)
-	mchk_logout(icsr, ICSR)
-	mchk_logout(pal_base, PAL_BASE)
-	mchk_logout(exc_mask, EXC_MASK)
-	mchk_logout(exc_sum, EXC_SUM)
-
+//	mchk_logout(mm_stat, MM_STAT)
+//	mchk_logout(va, VA)			// Unlocks VA and MM_STAT
+//	mchk_logout(isr, ISR)
+//	mchk_logout(icsr, ICSR)
+//	mchk_logout(pal_base, PAL_BASE)
+//	mchk_logout(exc_mask, EXC_MASK)
+//	mchk_logout(exc_sum, EXC_SUM)
+
+    mfpr	r25, mm_stat 
+	stqp	r25, CNS_Q_MM_STAT(r14)
+    mfpr	r25, va 
+	stqp	r25, CNS_Q_VA(r14)
+    mfpr	r25, isr 
+	stqp	r25, CNS_Q_ISR(r14)
+    mfpr	r25, icsr 
+	stqp	r25, CNS_Q_ICSR(r14)
+    mfpr	r25, pal_base 
+	stqp	r25, CNS_Q_PAL_BASE(r14)
+    mfpr	r25, exc_mask 
+	stqp	r25, CNS_Q_EXC_MASK(r14)
+    mfpr	r25, exc_sum 
+	stqp	r25, CNS_Q_EXC_SUM(r14)
+
+
+
+    
+    
 	ldah	r13, 0xfff0(r31)
 	zap	r13, 0xE0, r13			// Get Cbox IPR base
 	ldqp	r13, ld_lock(r13)		// Get ld_lock IPR
@@ -1278,31 +1297,81 @@ sys_mchk_write_logout_frame:
 	mfpr	r25, pt/**/n ;\
 	stqp	r25, CNS_Q_PT+(8*n)(r14)
 	
-	svpt(0)
-	svpt(1)
-	svpt(2)
-	svpt(3)
-	svpt(4)
-	svpt(5)
-	svpt(6)
-	svpt(7)
-	svpt(8)
-	svpt(9)
-	svpt(10)
-	svpt(11)
-	svpt(12)
-	svpt(13)
-	svpt(14)
-	svpt(15)
-	svpt(16)
-	svpt(17)
-	svpt(18)
-	svpt(19)
-	svpt(20)
-	svpt(21)
-	svpt(22)
-	svpt(23)
-	
+	mfpr	r25, pt0 
+	stqp	r25, CNS_Q_PT+(8*0)(r14)
+	mfpr	r25, pt1 
+	stqp	r25, CNS_Q_PT+(8*1)(r14)
+	mfpr	r25, pt2 
+	stqp	r25, CNS_Q_PT+(8*2)(r14)
+	mfpr	r25, pt3 
+	stqp	r25, CNS_Q_PT+(8*3)(r14)
+	mfpr	r25, pt4 
+	stqp	r25, CNS_Q_PT+(8*4)(r14)
+	mfpr	r25, pt5 
+	stqp	r25, CNS_Q_PT+(8*5)(r14)
+	mfpr	r25, pt6 
+	stqp	r25, CNS_Q_PT+(8*6)(r14)
+	mfpr	r25, pt7 
+	stqp	r25, CNS_Q_PT+(8*7)(r14)
+	mfpr	r25, pt8 
+	stqp	r25, CNS_Q_PT+(8*8)(r14)
+	mfpr	r25, pt9 
+	stqp	r25, CNS_Q_PT+(8*9)(r14)
+	mfpr	r25, pt10
+	stqp	r25, CNS_Q_PT+(8*10)(r14)
+	mfpr	r25, pt11
+	stqp	r25, CNS_Q_PT+(8*11)(r14)
+	mfpr	r25, pt12
+	stqp	r25, CNS_Q_PT+(8*12)(r14)
+	mfpr	r25, pt13
+	stqp	r25, CNS_Q_PT+(8*13)(r14)
+	mfpr	r25, pt14
+	stqp	r25, CNS_Q_PT+(8*14)(r14)
+	mfpr	r25, pt15
+	stqp	r25, CNS_Q_PT+(8*15)(r14)
+	mfpr	r25, pt16
+	stqp	r25, CNS_Q_PT+(8*16)(r14)
+	mfpr	r25, pt17
+	stqp	r25, CNS_Q_PT+(8*17)(r14)
+	mfpr	r25, pt18
+	stqp	r25, CNS_Q_PT+(8*18)(r14)
+	mfpr	r25, pt19
+	stqp	r25, CNS_Q_PT+(8*19)(r14)
+	mfpr	r25, pt20
+	stqp	r25, CNS_Q_PT+(8*20)(r14)
+	mfpr	r25, pt21
+	stqp	r25, CNS_Q_PT+(8*21)(r14)
+	mfpr	r25, pt22
+	stqp	r25, CNS_Q_PT+(8*22)(r14)
+	mfpr	r25, pt23
+	stqp	r25, CNS_Q_PT+(8*23)(r14)
+
+    
+//    svpt(0)
+//	svpt(1)
+//	svpt(2)
+//	svpt(3)
+//	svpt(4)
+//	svpt(5)
+//	svpt(6)
+//	svpt(7)
+//	svpt(8)
+//	svpt(9)
+//	svpt(10)
+//	svpt(11)
+//	svpt(12)
+//	svpt(13)
+//	svpt(14)
+//	svpt(15)
+//	svpt(16)
+//	svpt(17)
+//	svpt(18)
+//	svpt(19)
+//	svpt(20)
+//	svpt(21)
+//	svpt(22)
+//	svpt(23)
+//	
 	//+
 	// Log system specific info here
 	//-
diff --git a/system/alpha/palcode/platform_tlaser.s b/system/alpha/palcode/platform_tlaser.s
index 000ed9f38..d5a8b9fdd 100644
--- a/system/alpha/palcode/platform_tlaser.s
+++ b/system/alpha/palcode/platform_tlaser.s
@@ -1,6 +1,8 @@
 // build_fixed_image: not sure what means
 // real_mm to be replaced during rewrite
 // remove_save_state  remove_restore_state can be remooved to save space ??
+
+
 #define egore 0
 #define acore 0
 #define beh_model 0
@@ -30,7 +32,8 @@
 #include "fromHudsonOsf.h"
 #include "dc21164FromGasSources.h"
 #include "cserve.h"
-#include "simos.h"
+#include "tlaserreg.h"
+//#include "simos.h"
 
         
 #define ldlp ldl_p
@@ -158,10 +161,10 @@ _x:
 	sll	_rsum,22,_rsum;		\
 	addq	_raddr,_rsum,_raddr;	\
 	blbs	_scratch,1f;		\
-	lda	_raddr,tlep_lintrsum0_offset(_raddr); \
+	lda	_raddr,0x1180(_raddr); \
 	br	r31,2f;			\
 1: 					\
-	lda	_raddr,tlep_lintrsum1_offset(_raddr); \
+	lda	_raddr,0x11c0(_raddr); \
 2:      ldlp    _rsum,0(_raddr)
 	
 
@@ -211,9 +214,9 @@ _x:
 	lda	_raddr,0xff88(zero);	\
 	sll	_raddr,24,_raddr;	\
 	blbs	_whami,1f;		\
-	lda	_raddr,tlep_tlintrsum0_offset(_raddr);\
+	lda	_raddr,0x1180(_raddr);\
 	br	zero,2f;		\
-1:	lda	_raddr,tlep_tlintrsum1_offset(_raddr);\
+1:	lda	_raddr,0x11c0(_raddr);\
 2:	srl	_whami,1,_whami;	\
 	addq	_raddr,_whami,_raddr;	\
 	mb;				\
@@ -442,7 +445,7 @@ EXPORT(sys_wripir)
 //++
 // Send out the IP Intr
 //--
-	stqp	r14, TLSB_TLIPINTR_OFFSET(r13)	// Write to TLIPINTR reg
+	stqp	r14, 0x40(r13)	// Write to TLIPINTR reg WAS  TLSB_TLIPINTR_OFFSET  
 	wmb				// Push out the store
 
 	hw_rei
@@ -739,7 +742,7 @@ sys_int_23:
 	beq	r14, 1f
 
 	Get_TLSB_Node_Address(r14,r10)
-	lda	r10, tlsb_tlilid3_offset(r10)	// Get base TLILID address
+	lda	r10, 0xac0(r10)	// Get base TLILID address
 
 	ldlp	r13, 0(r10)			// Read the TLILID register
 	bne	r13, pal_post_dev_interrupt
@@ -763,7 +766,7 @@ sys_int_22:
 	beq	r14, 1f
 
 	Get_TLSB_Node_Address(r14,r10)
-	lda	r10, tlsb_tlilid2_offset(r10)	// Get base TLILID address
+	lda	r10, 0xa80(r10)	// Get base TLILID address
 
 	ldlp	r13, 0(r10)			// Read the TLILID register
 #if turbo_pcia_intr_fix == 0        
@@ -792,7 +795,7 @@ sys_int_21:
 	beq	r14, 1f
 
 	Get_TLSB_Node_Address(r14,r10)
-	lda	r10, tlsb_tlilid1_offset(r10)	// Get base TLILID address
+	lda	r10, 0xa40(r10)	// Get base TLILID address
 
 	ldlp	r13, 0(r10)			// Read the TLILID register
 #if turbo_pcia_intr_fix == 0        
@@ -954,7 +957,7 @@ tlep_ecc:
 	srl	r14, 1, r14			// shift off cpu number
 	Get_TLSB_Node_Address(r14,r10)		// compute our nodespace address
 
-	ldlp	r13, tlsb_tlber_offset(r10)	// read our TLBER
+	ldlp	r13, 0x40(r10)	// read our TLBER WAS tlsb_tlber_offset
 	srl	r13, 17, r13			// shift down the CWDE/CRDE bits
 
 	and	r13, 3, r13			// mask the CWDE/CRDE bits
@@ -1515,7 +1518,7 @@ sys_reset:
 	lda	r11, 0x7(r31)		// Set shadow copy of PS - kern mode, IPL=7
 	lda	r1, 0x1F(r31)		
 	mtpr	r1, ipl			// set internal <ipl>=1F
-	mtpr	r31, ps			// set new ps<cm>=0, Ibox copy
+	mtpr	r31, ev5__ps			// set new ps<cm>=0, Ibox copy
 	mtpr	r31, dtb_cm		// set new ps<cm>=0, Mbox copy
 
 	// Create the PALtemp pt_intmask -
@@ -1591,7 +1594,8 @@ sys_reset:
 	mtpr	r1, pt_scbb		// load scbb
 	mtpr	r31, pt_prbr		// clear out prbr
 #ifdef SIMOS
-        or      zero,kludge_initial_pcbb,r1
+//        or      zero,kludge_initial_pcbb,r1
+        GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
 #else
 	mfpr	r1, pal_base
 //orig	sget_addr r1, (kludge_initial_pcbb-pal$base), r1, verify=0// get address for temp pcbb
@@ -1849,7 +1853,8 @@ EXPORT(sys_machine_check)
 	lda	r0, scb_v_procmchk(r31)		// SCB vector
 	mfpr	r13, pt_mces			// Get MCES
 	sll	r0, 16, r0			// Move SCBv to correct position
-	bis	r13, #<1@mces$v_mchk>, r14	// Set MCES<MCHK> bit
+//	bis	r13, #<1@mces$v_mchk>, r14	// Set MCES<MCHK> bit
+	bis	r13, BIT(mces_v_mchk), r14	// Set MCES<MCHK> bit
 
 
 	zap	r14, 0x3C, r14			// Clear mchk_code word and SCBv word 
@@ -1979,9 +1984,11 @@ EXPORT(sys_mchk_collect_iprs)
 	and	r25, r4, r4
 	bne	r4, sys_cpu_mchk_not_retryable
 	
-	bis	r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
+//	bis	r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
+	bis	r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
 	and	r25, r4, r4				// Isolate the Uncorrectable Error Bit
-	bis	r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
+//	bis	r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
+	bis	r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
 	cmovne	r6, 0, r4				// r4 = 0 if IRD or if No Uncorrectable Error
         bne     r4, sys_cpu_mchk_not_retryable		
 
@@ -2360,7 +2367,7 @@ sys_post_mchk_trap:
 	bge	r25, 3f	
 
 	mtpr	r31, dtb_cm
-	mtpr	r31, ps
+	mtpr	r31, ev5__ps
 
 	mtpr	r30, pt_usp		// save user stack
 	mfpr	r30, pt_ksp
diff --git a/system/alpha/palcode/tlaserreg.h b/system/alpha/palcode/tlaserreg.h
new file mode 100644
index 000000000..7a8d9d9cc
--- /dev/null
+++ b/system/alpha/palcode/tlaserreg.h
@@ -0,0 +1,171 @@
+/* $Id: tlaserreg.h,v 1.3 2002/10/27 14:28:17 binkertn Exp $ */
+/*
+ * Copyright (C) 1998 by the Board of Trustees
+ *    of Leland Stanford Junior University.
+ * Copyright (C) 1998 Digital Equipment Corporation
+ *
+ * This file is part of the SimOS distribution.
+ * See LICENSE file for terms of the license.
+ *
+ */
+
+#ifndef __TLASERREG_H__
+#define __TLASERREG_H__
+
+///////////////////////////////////////////////////////////////////////
+//
+// This file is also included to build the palcode
+//
+
+// Common module defines
+#define TLDEV_REG		0x00
+#define TLBER_REG		0x40
+#define TLCNR_REG		0x80
+#define TLFADR0_REG		0x600
+#define TLFADR1_REG		0x640
+#define TLESR0_REG		0x680
+#define TLESR1_REG		0x6c0
+#define TLESR2_REG		0x700
+#define TLESR3_REG		0x740
+
+// I/O Module defines
+#define TLMMR0_REG		0x200
+#define TLMMR1_REG		0x240
+#define TLMMR2_REG		0x280
+#define TLMMR3_REG		0x2c0
+#define TLMMR4_REG		0x300
+#define TLMMR5_REG		0x340
+#define TLMMR6_REG		0x380
+#define TLMMR7_REG		0x3c0
+#define TLCPUMASK_REG		0x0b00
+#define TLILID0_REG		0xa00
+#define TLILID1_REG		0xa40
+#define TLILID2_REG		0xa80
+#define TLILID3_REG		0xac0
+#define TLMBPR_REG		0xc00
+#define ICCMSR_REG		0x2000
+#define ICCMTR_REG		0x20c0
+#define ICCWTR_REG		0x2100
+#define ICCNSE_REG		0x2040
+#define IDPNSE0_REG		0x2a40
+#define IDPNSE1_REG		0x2140
+#define IDPNSE2_REG		0x2240
+#define IDPNSE3_REG		0x2340
+#define IDPVR_REG		0x2b40
+#define IDPDR0_REG		0x2a80
+#define IDPDR1_REG		0x2180
+#define IDPDR2_REG		0x2280
+#define IDPDR3_REG		0x2380
+
+// CPU Module defines
+#define CPU0_OFFSET		0x0000
+#define CPU1_OFFSET		0x0040
+#define TLVID_REG		0x00c0
+#define TLDIAG_REG		0x1000
+#define TLMODCONFIG_REG		0x10c0
+#define TLINTRMASK0_REG		0x1100
+#define TLINTRMASK1_REG		0x1140
+#define TLINTRSUM0_REG		0x1180
+#define TLINTRSUM1_REG		0x11c0
+#define TLEPAERR_REG		0x1500
+#define TLEPDERR_REG		0x1540
+#define TLEPMERR_REG		0x1580
+#define TLEP_VMG_REG		0x15c0
+#define TLEPWERR_REG		0x1600
+
+// Memory Module defines
+#define MCR_REG			0x1880
+#define MIR_REG			0x1840
+#define MDRA_REG		0x1980
+#define MER_REG			0x1940
+#define DDR0_REG		0x10140
+#define DDR1_REG		0x14140
+#define DDR2_REG		0x18140
+#define DDR3_REG		0x1c140
+
+// Broadcast defines
+#define BROADCAST_NODE		0x18
+#define TLIPINTR_REG		0x40
+
+// GBUS defines
+#define GBUS_BASE		ULL(0xfffffcff90000000)
+#define GBUS_BIT_SHIFT		0x06
+#define FLASH_BASE		0x07000000
+#define UART_BASE		0x10000000
+#define WATCH_CSR_BASE		0x20000000
+#define WHATAMI_REG		0x30000000
+#define MISCR_REG		0x34000000
+#define SERNUM_REG		0x37000000
+
+// RTC defines
+#define RTC_SECOND		0	// second of minute [0..59]
+#define RTC_SECOND_ALARM	1	// seconds to alarm
+#define RTC_MINUTE		2	// minute of hour [0..59]
+#define RTC_MINUTE_ALARM	3	// minutes to alarm
+#define RTC_HOUR		4	// hour of day [0..23]
+#define RTC_HOUR_ALARM		5	// hours to alarm
+#define RTC_DAY_OF_WEEK		6	// day of week [1..7]
+#define RTC_DAY_OF_MONTH	7	// day of month [1..31]
+#define RTC_MONTH		8	// month of year [1..12]
+#define RTC_YEAR		9	// year [00..99]
+#define RTC_CONTROL_REGISTERA	10	// control register A
+#define RTC_CONTROL_REGISTERB	11	// control register B
+#define RTC_CONTROL_REGISTERC	12	// control register C
+#define RTC_CONTROL_REGISTERD	13	// control register D
+#define RTC_REGNUMBER_RTC_CR1	0x6A	// control register 1
+
+// Other defines
+#define DEVICE_TYPE_TIOP	0x2000
+#define DEVICE_TYPE_MEM		0x4000
+#define DEVICE_TYPE_CPU		0x8000
+
+
+///////////////////////////////////////////////////////////////////////
+//
+// litterals used in the platform_tlaser.s file.
+//
+// -DBUILD_PALCODE is only defined then. The compilation does include
+// this file from the simulation source tree.
+//
+// It is NOT an obsolete compilation option
+//
+
+#ifdef BUILD_PALCODE
+
+#define  tlep_lintrsum0_offset   0x1180
+#define  tlep_lintrsum1_offset   0x11c0
+#define  tlep_tlintrsum0_offset  tlep_lintrsum0_offset
+#define  tlep_tlintrsum1_offset  tlep_lintrsum1_offset
+#define  tlep_watch_csrc_offset  (RTC_CONTROL_REGISTERC <<GBUS_BIT_SHIFT)
+
+#define  tlsb_tlber              TLBER_REG
+#define  tlsb_tlber_offset       tlsb_tlber /* ??? */
+#define  tlsb_tldev              TLDEV_REG
+#define  tlsb_tlesr0             TLESR0_REG
+#define  tlsb_tlesr1             TLESR1_REG
+#define  tlsb_tlesr2             TLESR2_REG
+#define  tlsb_tlesr3             TLESR3_REG
+
+
+#define  tlsb_tlilid0_offset     TLILID0_REG
+#define  tlsb_tlilid1_offset     TLILID1_REG
+#define  tlsb_tlilid2_offset     TLILID2_REG
+#define  tlsb_tlilid3_offset     TLILID3_REG
+
+#define TLSB_TLIPINTR_OFFSET     TLIPINTR_REG
+
+#endif // BUILD_PALCODE
+
+
+
+///////////////////////////////////////////////////////////////////////
+//
+// Codes used to probe/clear the TLINTRSUM register
+//
+
+#define TLASER_INTRSUM_UART	1	// uart
+#define TLASER_INTRSUM_IPI	0x20	// IPI
+#define TLASER_INTRSUM_INTIM	0x40	// clock
+
+#endif // __TLASERREG_H__
+