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authorNathan Binkert <binkertn@umich.edu>2005-06-29 22:15:32 -0400
committerNathan Binkert <binkertn@umich.edu>2005-06-29 22:15:32 -0400
commite61899cbbf28c18578114ab4a7c99ce00fa39067 (patch)
tree1814c3ed076eec384626450dd1fe873f922f18f9 /system/alpha
parentfce2978d4182b2c2434c1742c1de613b7747deed (diff)
downloadgem5-e61899cbbf28c18578114ab4a7c99ce00fa39067.tar.xz
Add missing TSUNAMI ipi code.
Diffstat (limited to 'system/alpha')
-rw-r--r--system/alpha/palcode/platform.S17
1 files changed, 17 insertions, 0 deletions
diff --git a/system/alpha/palcode/platform.S b/system/alpha/palcode/platform.S
index 5c4254fd3..6ed97f2d8 100644
--- a/system/alpha/palcode/platform.S
+++ b/system/alpha/palcode/platform.S
@@ -313,17 +313,34 @@ EXPORT(sys_wripir)
and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported
bis r31, 0x1, r16 // get a one
sll r16, r14, r14 // shift the bit to the right place
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ sll r14,IPIQ_shift,r14
+#endif
+
//
// Build the Broadcast Space base address
//
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ lda r16,0xf01(r31)
+ sll r16,32,r16
+ ldah r13,0xa0(r31)
+ sll r13,8,r13
+ bis r16,r13,r16
+ lda r16,IPIQ_addr(r16)
+#elif defined(TLASER)
lda r13, 0xff8e(r31) // Load the upper address bits
sll r13, 24, r13 // shift them to the top
+#endif
//
// Send out the IP Intr
//
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ stq_p r14, 0(r16) // Tsunami MISC Register
+#elif defined(TLASER)
stq_p r14, 0x40(r13) // Write to TLIPINTR reg
+#endif
wmb // Push out the store
hw_rei