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authorMatt Evans <Matt.Evans@arm.com>2012-09-07 14:20:53 -0500
committerMatt Evans <Matt.Evans@arm.com>2012-09-07 14:20:53 -0500
commit25c1933ffe7943b057056f9c9822001443ceb4e8 (patch)
treefe9a430a57b9c77147d07f0e9b885e57646b6017 /system/arm/simple_bootloader
parent5217d5a451322199b4165ee0293ed2681dae5da3 (diff)
downloadgem5-25c1933ffe7943b057056f9c9822001443ceb4e8.tar.xz
ARM: Fix issue with with way MPIDR is read to include affinity levels.
The simple_bootloader checks for CPU0 in a manner incompatible with systems actually using affinity levels -- just looking at MPIDR[7:0]. However, in future we may wish to use real affinity levels and this method will be in danger of matching several CPUs with affinity0 = 0. Match affinity2 == affinity1 == affinity0 == 0 instead.
Diffstat (limited to 'system/arm/simple_bootloader')
-rw-r--r--system/arm/simple_bootloader/simple.S3
1 files changed, 1 insertions, 2 deletions
diff --git a/system/arm/simple_bootloader/simple.S b/system/arm/simple_bootloader/simple.S
index afba47728..4870eccf8 100644
--- a/system/arm/simple_bootloader/simple.S
+++ b/system/arm/simple_bootloader/simple.S
@@ -68,8 +68,7 @@ _entry:
bootldr:
mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
- uxtb r8, r8 // isolate the lower 8 bits (affinity lvl 1)
- adds r8, r8, #0 // set flags for branch
+ bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels)
bxeq r3 // if it's 0 (CPU 0), branch to kernel
mov r8, #1
str r8, [r4, #0] // Enable CPU interface on GIC